Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * Sukumar Ghorai <s-ghorai@ti.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation's version 2 of |
| 12 | * the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <config.h> |
| 26 | #include <common.h> |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 27 | #include <malloc.h> |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 28 | #include <mmc.h> |
| 29 | #include <part.h> |
| 30 | #include <i2c.h> |
| 31 | #include <twl4030.h> |
Balaji T K | f843d33 | 2011-09-08 06:34:57 +0000 | [diff] [blame] | 32 | #include <twl6030.h> |
Nishanth Menon | 627612c | 2013-03-26 05:20:54 +0000 | [diff] [blame] | 33 | #include <palmas.h> |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 34 | #include <asm/io.h> |
| 35 | #include <asm/arch/mmc_host_def.h> |
Roger Quadros | 44157de | 2015-09-19 16:26:53 +0530 | [diff] [blame] | 36 | #if !defined(CONFIG_SOC_KEYSTONE) |
| 37 | #include <asm/gpio.h> |
Dirk Behme | 7414023 | 2011-05-15 09:04:47 +0000 | [diff] [blame] | 38 | #include <asm/arch/sys_proto.h> |
Roger Quadros | 44157de | 2015-09-19 16:26:53 +0530 | [diff] [blame] | 39 | #endif |
Tom Rini | df5338c | 2017-02-09 13:41:28 -0500 | [diff] [blame] | 40 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
| 41 | #include <asm/arch/mux.h> |
| 42 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 43 | #include <dm.h> |
| 44 | |
| 45 | DECLARE_GLOBAL_DATA_PTR; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 46 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 47 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
| 48 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ |
| 49 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) |
| 50 | #define OMAP_HSMMC_USE_GPIO |
| 51 | #else |
| 52 | #undef OMAP_HSMMC_USE_GPIO |
| 53 | #endif |
| 54 | |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 55 | /* common definitions for all OMAPs */ |
| 56 | #define SYSCTL_SRC (1 << 25) |
| 57 | #define SYSCTL_SRD (1 << 26) |
| 58 | |
Adam Ford | c0edb0f | 2017-04-17 08:09:37 -0500 | [diff] [blame] | 59 | struct omap2_mmc_platform_config { |
| 60 | u32 reg_offset; |
| 61 | }; |
| 62 | |
Nikita Kiryanov | 1382286 | 2012-12-03 02:19:43 +0000 | [diff] [blame] | 63 | struct omap_hsmmc_data { |
| 64 | struct hsmmc *base_addr; |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 65 | #ifndef CONFIG_DM_MMC |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 66 | struct mmc_config cfg; |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 67 | #endif |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 68 | #ifdef OMAP_HSMMC_USE_GPIO |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 69 | #ifdef CONFIG_DM_MMC |
| 70 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ |
| 71 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ |
| 72 | bool cd_inverted; |
| 73 | #else |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 74 | int cd_gpio; |
Nikita Kiryanov | 4be9dbc | 2012-12-03 02:19:47 +0000 | [diff] [blame] | 75 | int wp_gpio; |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 76 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 77 | #endif |
Nikita Kiryanov | 1382286 | 2012-12-03 02:19:43 +0000 | [diff] [blame] | 78 | }; |
| 79 | |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 80 | /* If we fail after 1 second wait, something is really bad */ |
| 81 | #define MAX_RETRY_MS 1000 |
| 82 | |
Sricharan | f72611f | 2011-11-15 09:49:53 -0500 | [diff] [blame] | 83 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
| 84 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
| 85 | unsigned int siz); |
Balaji T K | f843d33 | 2011-09-08 06:34:57 +0000 | [diff] [blame] | 86 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 87 | static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) |
| 88 | { |
| 89 | #ifdef CONFIG_DM_MMC |
| 90 | return dev_get_priv(mmc->dev); |
| 91 | #else |
| 92 | return (struct omap_hsmmc_data *)mmc->priv; |
| 93 | #endif |
| 94 | } |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 95 | static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) |
| 96 | { |
| 97 | #ifdef CONFIG_DM_MMC |
| 98 | struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); |
| 99 | return &plat->cfg; |
| 100 | #else |
| 101 | return &((struct omap_hsmmc_data *)mmc->priv)->cfg; |
| 102 | #endif |
| 103 | } |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 104 | |
| 105 | #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 106 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
| 107 | { |
Simon Glass | 1a96d7f | 2014-10-22 21:37:09 -0600 | [diff] [blame] | 108 | int ret; |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 109 | |
Simon Glass | 1a96d7f | 2014-10-22 21:37:09 -0600 | [diff] [blame] | 110 | #ifndef CONFIG_DM_GPIO |
| 111 | if (!gpio_is_valid(gpio)) |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 112 | return -1; |
Simon Glass | 1a96d7f | 2014-10-22 21:37:09 -0600 | [diff] [blame] | 113 | #endif |
| 114 | ret = gpio_request(gpio, label); |
| 115 | if (ret) |
| 116 | return ret; |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 117 | |
Simon Glass | 1a96d7f | 2014-10-22 21:37:09 -0600 | [diff] [blame] | 118 | ret = gpio_direction_input(gpio); |
| 119 | if (ret) |
| 120 | return ret; |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 121 | |
| 122 | return gpio; |
| 123 | } |
Nikita Kiryanov | 4eae05c | 2012-12-03 02:19:44 +0000 | [diff] [blame] | 124 | #endif |
| 125 | |
Jeroen Hofstee | aedeeaa | 2014-07-12 21:24:08 +0200 | [diff] [blame] | 126 | static unsigned char mmc_board_init(struct mmc *mmc) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 127 | { |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 128 | #if defined(CONFIG_OMAP34XX) |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 129 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 130 | t2_t *t2_base = (t2_t *)T2_BASE; |
| 131 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; |
Grazvydas Ignotas | ef2b729 | 2012-03-19 03:50:53 +0000 | [diff] [blame] | 132 | u32 pbias_lite; |
Adam Ford | ef35496 | 2017-02-06 11:31:43 -0600 | [diff] [blame] | 133 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
| 134 | u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); |
| 135 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 136 | |
Grazvydas Ignotas | ef2b729 | 2012-03-19 03:50:53 +0000 | [diff] [blame] | 137 | pbias_lite = readl(&t2_base->pbias_lite); |
| 138 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); |
Albert ARIBAUD \(3ADEV\) | 6ad0981 | 2015-01-16 09:09:50 +0100 | [diff] [blame] | 139 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
| 140 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ |
| 141 | pbias_lite &= ~PBIASLITEVMODE0; |
| 142 | #endif |
Adam Ford | ef35496 | 2017-02-06 11:31:43 -0600 | [diff] [blame] | 143 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
| 144 | if (get_cpu_family() == CPU_OMAP36XX) { |
| 145 | /* Disable extended drain IO before changing PBIAS */ |
| 146 | wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; |
| 147 | writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); |
| 148 | } |
| 149 | #endif |
Grazvydas Ignotas | ef2b729 | 2012-03-19 03:50:53 +0000 | [diff] [blame] | 150 | writel(pbias_lite, &t2_base->pbias_lite); |
Paul Kocialkowski | 6955989 | 2014-11-08 20:55:47 +0100 | [diff] [blame] | 151 | |
Grazvydas Ignotas | ef2b729 | 2012-03-19 03:50:53 +0000 | [diff] [blame] | 152 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 153 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
| 154 | &t2_base->pbias_lite); |
| 155 | |
Adam Ford | ef35496 | 2017-02-06 11:31:43 -0600 | [diff] [blame] | 156 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
| 157 | if (get_cpu_family() == CPU_OMAP36XX) |
| 158 | /* Enable extended drain IO after changing PBIAS */ |
| 159 | writel(wkup_ctrl | |
| 160 | OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, |
| 161 | OMAP34XX_CTRL_WKUP_CTRL); |
| 162 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 163 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
| 164 | &t2_base->devconf0); |
| 165 | |
| 166 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, |
| 167 | &t2_base->devconf1); |
| 168 | |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 169 | /* Change from default of 52MHz to 26MHz if necessary */ |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 170 | if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 171 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
| 172 | &t2_base->ctl_prog_io1); |
| 173 | |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 174 | writel(readl(&prcm_base->fclken1_core) | |
| 175 | EN_MMC1 | EN_MMC2 | EN_MMC3, |
| 176 | &prcm_base->fclken1_core); |
| 177 | |
| 178 | writel(readl(&prcm_base->iclken1_core) | |
| 179 | EN_MMC1 | EN_MMC2 | EN_MMC3, |
| 180 | &prcm_base->iclken1_core); |
| 181 | #endif |
| 182 | |
Lokesh Vutla | d999d05 | 2016-11-23 13:25:28 +0530 | [diff] [blame] | 183 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
Balaji T K | f843d33 | 2011-09-08 06:34:57 +0000 | [diff] [blame] | 184 | /* PBIAS config needed for MMC1 only */ |
Jean-Jacques Hiblot | 26319b1 | 2017-03-22 16:00:32 +0100 | [diff] [blame] | 185 | if (mmc_get_blk_desc(mmc)->devnum == 0) |
Lokesh Vutla | d999d05 | 2016-11-23 13:25:28 +0530 | [diff] [blame] | 186 | vmmc_pbias_config(LDO_VOLT_3V0); |
Balaji T K | d9cf836 | 2012-03-12 02:25:49 +0000 | [diff] [blame] | 187 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
Sricharan | f72611f | 2011-11-15 09:49:53 -0500 | [diff] [blame] | 192 | void mmc_init_stream(struct hsmmc *mmc_base) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 193 | { |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 194 | ulong start; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 195 | |
| 196 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); |
| 197 | |
| 198 | writel(MMC_CMD0, &mmc_base->cmd); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 199 | start = get_timer(0); |
| 200 | while (!(readl(&mmc_base->stat) & CC_MASK)) { |
| 201 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 202 | printf("%s: timedout waiting for cc!\n", __func__); |
| 203 | return; |
| 204 | } |
| 205 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 206 | writel(CC_MASK, &mmc_base->stat) |
| 207 | ; |
| 208 | writel(MMC_CMD0, &mmc_base->cmd) |
| 209 | ; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 210 | start = get_timer(0); |
| 211 | while (!(readl(&mmc_base->stat) & CC_MASK)) { |
| 212 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 213 | printf("%s: timedout waiting for cc2!\n", __func__); |
| 214 | return; |
| 215 | } |
| 216 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 217 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
| 218 | } |
| 219 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 220 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 221 | { |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 222 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
Nikita Kiryanov | 1382286 | 2012-12-03 02:19:43 +0000 | [diff] [blame] | 223 | struct hsmmc *mmc_base; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 224 | unsigned int reg_val; |
| 225 | unsigned int dsor; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 226 | ulong start; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 227 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 228 | mmc_base = priv->base_addr; |
Balaji T K | f843d33 | 2011-09-08 06:34:57 +0000 | [diff] [blame] | 229 | mmc_board_init(mmc); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 230 | |
| 231 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, |
| 232 | &mmc_base->sysconfig); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 233 | start = get_timer(0); |
| 234 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { |
| 235 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 236 | printf("%s: timedout waiting for cc2!\n", __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 237 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 238 | } |
| 239 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 240 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 241 | start = get_timer(0); |
| 242 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { |
| 243 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 244 | printf("%s: timedout waiting for softresetall!\n", |
| 245 | __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 246 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 247 | } |
| 248 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 249 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
| 250 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, |
| 251 | &mmc_base->capa); |
| 252 | |
| 253 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; |
| 254 | |
| 255 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | |
| 256 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | |
| 257 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); |
| 258 | |
| 259 | dsor = 240; |
| 260 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), |
| 261 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); |
| 262 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, |
| 263 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 264 | start = get_timer(0); |
| 265 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { |
| 266 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 267 | printf("%s: timedout waiting for ics!\n", __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 268 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 269 | } |
| 270 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 271 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
| 272 | |
| 273 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); |
| 274 | |
| 275 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | |
| 276 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, |
| 277 | &mmc_base->ie); |
| 278 | |
| 279 | mmc_init_stream(mmc_base); |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 284 | /* |
| 285 | * MMC controller internal finite state machine reset |
| 286 | * |
| 287 | * Used to reset command or data internal state machines, using respectively |
| 288 | * SRC or SRD bit of SYSCTL register |
| 289 | */ |
| 290 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) |
| 291 | { |
| 292 | ulong start; |
| 293 | |
| 294 | mmc_reg_out(&mmc_base->sysctl, bit, bit); |
| 295 | |
Oleksandr Tyshchenko | 06640ca | 2013-08-06 13:44:16 +0300 | [diff] [blame] | 296 | /* |
| 297 | * CMD(DAT) lines reset procedures are slightly different |
| 298 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). |
| 299 | * According to OMAP3 TRM: |
| 300 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it |
| 301 | * returns to 0x0. |
| 302 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset |
| 303 | * procedure steps must be as follows: |
| 304 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in |
| 305 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). |
| 306 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. |
| 307 | * 3. Wait until the SRC (SRD) bit returns to 0x0 |
| 308 | * (reset procedure is completed). |
| 309 | */ |
| 310 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
Nikita Kiryanov | 5ffdd85 | 2015-07-30 23:56:20 +0300 | [diff] [blame] | 311 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
Oleksandr Tyshchenko | 06640ca | 2013-08-06 13:44:16 +0300 | [diff] [blame] | 312 | if (!(readl(&mmc_base->sysctl) & bit)) { |
| 313 | start = get_timer(0); |
| 314 | while (!(readl(&mmc_base->sysctl) & bit)) { |
| 315 | if (get_timer(0) - start > MAX_RETRY_MS) |
| 316 | return; |
| 317 | } |
| 318 | } |
| 319 | #endif |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 320 | start = get_timer(0); |
| 321 | while ((readl(&mmc_base->sysctl) & bit) != 0) { |
| 322 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 323 | printf("%s: timedout waiting for sysctl %x to clear\n", |
| 324 | __func__, bit); |
| 325 | return; |
| 326 | } |
| 327 | } |
| 328 | } |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 329 | #ifndef CONFIG_DM_MMC |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 330 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 331 | struct mmc_data *data) |
| 332 | { |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 333 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 334 | #else |
| 335 | static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 336 | struct mmc_data *data) |
| 337 | { |
| 338 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
| 339 | #endif |
Nikita Kiryanov | 1382286 | 2012-12-03 02:19:43 +0000 | [diff] [blame] | 340 | struct hsmmc *mmc_base; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 341 | unsigned int flags, mmc_stat; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 342 | ulong start; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 343 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 344 | mmc_base = priv->base_addr; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 345 | start = get_timer(0); |
Tom Rini | 32ec325 | 2012-01-30 11:22:25 +0000 | [diff] [blame] | 346 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 347 | if (get_timer(0) - start > MAX_RETRY_MS) { |
Tom Rini | 32ec325 | 2012-01-30 11:22:25 +0000 | [diff] [blame] | 348 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
| 349 | __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 350 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 351 | } |
| 352 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 353 | writel(0xFFFFFFFF, &mmc_base->stat); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 354 | start = get_timer(0); |
| 355 | while (readl(&mmc_base->stat)) { |
| 356 | if (get_timer(0) - start > MAX_RETRY_MS) { |
Grazvydas Ignotas | 8927ac9 | 2012-03-19 12:11:43 +0000 | [diff] [blame] | 357 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
| 358 | __func__, readl(&mmc_base->stat)); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 359 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 360 | } |
| 361 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 362 | /* |
| 363 | * CMDREG |
| 364 | * CMDIDX[13:8] : Command index |
| 365 | * DATAPRNT[5] : Data Present Select |
| 366 | * ENCMDIDX[4] : Command Index Check Enable |
| 367 | * ENCMDCRC[3] : Command CRC Check Enable |
| 368 | * RSPTYP[1:0] |
| 369 | * 00 = No Response |
| 370 | * 01 = Length 136 |
| 371 | * 10 = Length 48 |
| 372 | * 11 = Length 48 Check busy after response |
| 373 | */ |
| 374 | /* Delay added before checking the status of frq change |
| 375 | * retry not supported by mmc.c(core file) |
| 376 | */ |
| 377 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) |
| 378 | udelay(50000); /* wait 50 ms */ |
| 379 | |
| 380 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
| 381 | flags = 0; |
| 382 | else if (cmd->resp_type & MMC_RSP_136) |
| 383 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; |
| 384 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 385 | flags = RSP_TYPE_LGHT48B; |
| 386 | else |
| 387 | flags = RSP_TYPE_LGHT48; |
| 388 | |
| 389 | /* enable default flags */ |
| 390 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | |
| 391 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); |
| 392 | |
| 393 | if (cmd->resp_type & MMC_RSP_CRC) |
| 394 | flags |= CCCE_CHECK; |
| 395 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 396 | flags |= CICE_CHECK; |
| 397 | |
| 398 | if (data) { |
| 399 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || |
| 400 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { |
| 401 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); |
| 402 | data->blocksize = 512; |
| 403 | writel(data->blocksize | (data->blocks << 16), |
| 404 | &mmc_base->blk); |
| 405 | } else |
| 406 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); |
| 407 | |
| 408 | if (data->flags & MMC_DATA_READ) |
| 409 | flags |= (DP_DATA | DDIR_READ); |
| 410 | else |
| 411 | flags |= (DP_DATA | DDIR_WRITE); |
| 412 | } |
| 413 | |
| 414 | writel(cmd->cmdarg, &mmc_base->arg); |
Lubomir Popov | 19df412 | 2013-08-14 18:59:18 +0300 | [diff] [blame] | 415 | udelay(20); /* To fix "No status update" error on eMMC */ |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 416 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
| 417 | |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 418 | start = get_timer(0); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 419 | do { |
| 420 | mmc_stat = readl(&mmc_base->stat); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 421 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 422 | printf("%s : timeout: No status update\n", __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 423 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 424 | } |
| 425 | } while (!mmc_stat); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 426 | |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 427 | if ((mmc_stat & IE_CTO) != 0) { |
| 428 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 429 | return -ETIMEDOUT; |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 430 | } else if ((mmc_stat & ERRI_MASK) != 0) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 431 | return -1; |
| 432 | |
| 433 | if (mmc_stat & CC_MASK) { |
| 434 | writel(CC_MASK, &mmc_base->stat); |
| 435 | if (cmd->resp_type & MMC_RSP_PRESENT) { |
| 436 | if (cmd->resp_type & MMC_RSP_136) { |
| 437 | /* response type 2 */ |
| 438 | cmd->response[3] = readl(&mmc_base->rsp10); |
| 439 | cmd->response[2] = readl(&mmc_base->rsp32); |
| 440 | cmd->response[1] = readl(&mmc_base->rsp54); |
| 441 | cmd->response[0] = readl(&mmc_base->rsp76); |
| 442 | } else |
| 443 | /* response types 1, 1b, 3, 4, 5, 6 */ |
| 444 | cmd->response[0] = readl(&mmc_base->rsp10); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | if (data && (data->flags & MMC_DATA_READ)) { |
| 449 | mmc_read_data(mmc_base, data->dest, |
| 450 | data->blocksize * data->blocks); |
| 451 | } else if (data && (data->flags & MMC_DATA_WRITE)) { |
| 452 | mmc_write_data(mmc_base, data->src, |
| 453 | data->blocksize * data->blocks); |
| 454 | } |
| 455 | return 0; |
| 456 | } |
| 457 | |
Sricharan | f72611f | 2011-11-15 09:49:53 -0500 | [diff] [blame] | 458 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 459 | { |
| 460 | unsigned int *output_buf = (unsigned int *)buf; |
| 461 | unsigned int mmc_stat; |
| 462 | unsigned int count; |
| 463 | |
| 464 | /* |
| 465 | * Start Polled Read |
| 466 | */ |
| 467 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; |
| 468 | count /= 4; |
| 469 | |
| 470 | while (size) { |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 471 | ulong start = get_timer(0); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 472 | do { |
| 473 | mmc_stat = readl(&mmc_base->stat); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 474 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 475 | printf("%s: timedout waiting for status!\n", |
| 476 | __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 477 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 478 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 479 | } while (mmc_stat == 0); |
| 480 | |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 481 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
| 482 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); |
| 483 | |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 484 | if ((mmc_stat & ERRI_MASK) != 0) |
| 485 | return 1; |
| 486 | |
| 487 | if (mmc_stat & BRR_MASK) { |
| 488 | unsigned int k; |
| 489 | |
| 490 | writel(readl(&mmc_base->stat) | BRR_MASK, |
| 491 | &mmc_base->stat); |
| 492 | for (k = 0; k < count; k++) { |
| 493 | *output_buf = readl(&mmc_base->data); |
| 494 | output_buf++; |
| 495 | } |
| 496 | size -= (count*4); |
| 497 | } |
| 498 | |
| 499 | if (mmc_stat & BWR_MASK) |
| 500 | writel(readl(&mmc_base->stat) | BWR_MASK, |
| 501 | &mmc_base->stat); |
| 502 | |
| 503 | if (mmc_stat & TC_MASK) { |
| 504 | writel(readl(&mmc_base->stat) | TC_MASK, |
| 505 | &mmc_base->stat); |
| 506 | break; |
| 507 | } |
| 508 | } |
| 509 | return 0; |
| 510 | } |
| 511 | |
Sricharan | f72611f | 2011-11-15 09:49:53 -0500 | [diff] [blame] | 512 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
| 513 | unsigned int size) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 514 | { |
| 515 | unsigned int *input_buf = (unsigned int *)buf; |
| 516 | unsigned int mmc_stat; |
| 517 | unsigned int count; |
| 518 | |
| 519 | /* |
Lubomir Popov | 19df412 | 2013-08-14 18:59:18 +0300 | [diff] [blame] | 520 | * Start Polled Write |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 521 | */ |
| 522 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; |
| 523 | count /= 4; |
| 524 | |
| 525 | while (size) { |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 526 | ulong start = get_timer(0); |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 527 | do { |
| 528 | mmc_stat = readl(&mmc_base->stat); |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 529 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 530 | printf("%s: timedout waiting for status!\n", |
| 531 | __func__); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 532 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 533 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 534 | } while (mmc_stat == 0); |
| 535 | |
Grazvydas Ignotas | ddde188 | 2012-03-19 12:12:06 +0000 | [diff] [blame] | 536 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
| 537 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); |
| 538 | |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 539 | if ((mmc_stat & ERRI_MASK) != 0) |
| 540 | return 1; |
| 541 | |
| 542 | if (mmc_stat & BWR_MASK) { |
| 543 | unsigned int k; |
| 544 | |
| 545 | writel(readl(&mmc_base->stat) | BWR_MASK, |
| 546 | &mmc_base->stat); |
| 547 | for (k = 0; k < count; k++) { |
| 548 | writel(*input_buf, &mmc_base->data); |
| 549 | input_buf++; |
| 550 | } |
| 551 | size -= (count*4); |
| 552 | } |
| 553 | |
| 554 | if (mmc_stat & BRR_MASK) |
| 555 | writel(readl(&mmc_base->stat) | BRR_MASK, |
| 556 | &mmc_base->stat); |
| 557 | |
| 558 | if (mmc_stat & TC_MASK) { |
| 559 | writel(readl(&mmc_base->stat) | TC_MASK, |
| 560 | &mmc_base->stat); |
| 561 | break; |
| 562 | } |
| 563 | } |
| 564 | return 0; |
| 565 | } |
| 566 | |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 567 | #ifndef CONFIG_DM_MMC |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 568 | static int omap_hsmmc_set_ios(struct mmc *mmc) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 569 | { |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 570 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 571 | #else |
| 572 | static int omap_hsmmc_set_ios(struct udevice *dev) |
| 573 | { |
| 574 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
| 575 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 576 | struct mmc *mmc = upriv->mmc; |
| 577 | #endif |
Nikita Kiryanov | 1382286 | 2012-12-03 02:19:43 +0000 | [diff] [blame] | 578 | struct hsmmc *mmc_base; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 579 | unsigned int dsor = 0; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 580 | ulong start; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 581 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 582 | mmc_base = priv->base_addr; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 583 | /* configue bus width */ |
| 584 | switch (mmc->bus_width) { |
| 585 | case 8: |
| 586 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, |
| 587 | &mmc_base->con); |
| 588 | break; |
| 589 | |
| 590 | case 4: |
| 591 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, |
| 592 | &mmc_base->con); |
| 593 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, |
| 594 | &mmc_base->hctl); |
| 595 | break; |
| 596 | |
| 597 | case 1: |
| 598 | default: |
| 599 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, |
| 600 | &mmc_base->con); |
| 601 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, |
| 602 | &mmc_base->hctl); |
| 603 | break; |
| 604 | } |
| 605 | |
| 606 | /* configure clock with 96Mhz system clock. |
| 607 | */ |
| 608 | if (mmc->clock != 0) { |
| 609 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); |
| 610 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) |
| 611 | dsor++; |
| 612 | } |
| 613 | |
| 614 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), |
| 615 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); |
| 616 | |
| 617 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, |
| 618 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); |
| 619 | |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 620 | start = get_timer(0); |
| 621 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { |
| 622 | if (get_timer(0) - start > MAX_RETRY_MS) { |
| 623 | printf("%s: timedout waiting for ics!\n", __func__); |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 624 | return -ETIMEDOUT; |
Nishanth Menon | d3bfaac | 2010-11-19 11:18:12 -0500 | [diff] [blame] | 625 | } |
| 626 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 627 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 628 | |
| 629 | return 0; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 630 | } |
| 631 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 632 | #ifdef OMAP_HSMMC_USE_GPIO |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 633 | #ifdef CONFIG_DM_MMC |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 634 | static int omap_hsmmc_getcd(struct udevice *dev) |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 635 | { |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 636 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 637 | int value; |
| 638 | |
| 639 | value = dm_gpio_get_value(&priv->cd_gpio); |
| 640 | /* if no CD return as 1 */ |
| 641 | if (value < 0) |
| 642 | return 1; |
| 643 | |
| 644 | if (priv->cd_inverted) |
| 645 | return !value; |
| 646 | return value; |
| 647 | } |
| 648 | |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 649 | static int omap_hsmmc_getwp(struct udevice *dev) |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 650 | { |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 651 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 652 | int value; |
| 653 | |
| 654 | value = dm_gpio_get_value(&priv->wp_gpio); |
| 655 | /* if no WP return as 0 */ |
| 656 | if (value < 0) |
| 657 | return 0; |
| 658 | return value; |
| 659 | } |
| 660 | #else |
| 661 | static int omap_hsmmc_getcd(struct mmc *mmc) |
| 662 | { |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 663 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 664 | int cd_gpio; |
| 665 | |
| 666 | /* if no CD return as 1 */ |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 667 | cd_gpio = priv->cd_gpio; |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 668 | if (cd_gpio < 0) |
| 669 | return 1; |
| 670 | |
Igor Grinberg | 2f4e095 | 2014-11-03 11:32:23 +0200 | [diff] [blame] | 671 | /* NOTE: assumes card detect signal is active-low */ |
| 672 | return !gpio_get_value(cd_gpio); |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | static int omap_hsmmc_getwp(struct mmc *mmc) |
| 676 | { |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 677 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 678 | int wp_gpio; |
| 679 | |
| 680 | /* if no WP return as 0 */ |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 681 | wp_gpio = priv->wp_gpio; |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 682 | if (wp_gpio < 0) |
| 683 | return 0; |
| 684 | |
Igor Grinberg | 2f4e095 | 2014-11-03 11:32:23 +0200 | [diff] [blame] | 685 | /* NOTE: assumes write protect signal is active-high */ |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 686 | return gpio_get_value(wp_gpio); |
| 687 | } |
| 688 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 689 | #endif |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 690 | |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 691 | #ifdef CONFIG_DM_MMC |
| 692 | static const struct dm_mmc_ops omap_hsmmc_ops = { |
| 693 | .send_cmd = omap_hsmmc_send_cmd, |
| 694 | .set_ios = omap_hsmmc_set_ios, |
| 695 | #ifdef OMAP_HSMMC_USE_GPIO |
| 696 | .get_cd = omap_hsmmc_getcd, |
| 697 | .get_wp = omap_hsmmc_getwp, |
| 698 | #endif |
| 699 | }; |
| 700 | #else |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 701 | static const struct mmc_ops omap_hsmmc_ops = { |
| 702 | .send_cmd = omap_hsmmc_send_cmd, |
| 703 | .set_ios = omap_hsmmc_set_ios, |
| 704 | .init = omap_hsmmc_init_setup, |
| 705 | #ifdef OMAP_HSMMC_USE_GPIO |
| 706 | .getcd = omap_hsmmc_getcd, |
| 707 | .getwp = omap_hsmmc_getwp, |
| 708 | #endif |
| 709 | }; |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 710 | #endif |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 711 | |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 712 | #ifndef CONFIG_DM_MMC |
Nikita Kiryanov | 4be9dbc | 2012-12-03 02:19:47 +0000 | [diff] [blame] | 713 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
| 714 | int wp_gpio) |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 715 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 716 | struct mmc *mmc; |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 717 | struct omap_hsmmc_data *priv; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 718 | struct mmc_config *cfg; |
| 719 | uint host_caps_val; |
| 720 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 721 | priv = malloc(sizeof(*priv)); |
| 722 | if (priv == NULL) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 723 | return -1; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 724 | |
Rob Herring | 5fd3edd | 2015-03-23 17:56:59 -0500 | [diff] [blame] | 725 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 726 | |
| 727 | switch (dev_index) { |
| 728 | case 0: |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 729 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 730 | break; |
Tom Rini | fd6e294 | 2011-10-12 06:20:50 +0000 | [diff] [blame] | 731 | #ifdef OMAP_HSMMC2_BASE |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 732 | case 1: |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 733 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
Lubomir Popov | 19df412 | 2013-08-14 18:59:18 +0300 | [diff] [blame] | 734 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 735 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
Roger Quadros | 44157de | 2015-09-19 16:26:53 +0530 | [diff] [blame] | 736 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
| 737 | defined(CONFIG_HSMMC2_8BIT) |
Lubomir Popov | 19df412 | 2013-08-14 18:59:18 +0300 | [diff] [blame] | 738 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
| 739 | host_caps_val |= MMC_MODE_8BIT; |
| 740 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 741 | break; |
Tom Rini | fd6e294 | 2011-10-12 06:20:50 +0000 | [diff] [blame] | 742 | #endif |
| 743 | #ifdef OMAP_HSMMC3_BASE |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 744 | case 2: |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 745 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 746 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
Lubomir Popov | 19df412 | 2013-08-14 18:59:18 +0300 | [diff] [blame] | 747 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
| 748 | host_caps_val |= MMC_MODE_8BIT; |
| 749 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 750 | break; |
Tom Rini | fd6e294 | 2011-10-12 06:20:50 +0000 | [diff] [blame] | 751 | #endif |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 752 | default: |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 753 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 754 | return 1; |
| 755 | } |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 756 | #ifdef OMAP_HSMMC_USE_GPIO |
| 757 | /* on error gpio values are set to -1, which is what we want */ |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 758 | priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
| 759 | priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 760 | #endif |
Peter Korsgaard | 47c6b2a | 2013-03-21 04:00:04 +0000 | [diff] [blame] | 761 | |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 762 | cfg = &priv->cfg; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 763 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 764 | cfg->name = "OMAP SD/MMC"; |
| 765 | cfg->ops = &omap_hsmmc_ops; |
| 766 | |
| 767 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
| 768 | cfg->host_caps = host_caps_val & ~host_caps_mask; |
| 769 | |
| 770 | cfg->f_min = 400000; |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 771 | |
| 772 | if (f_max != 0) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 773 | cfg->f_max = f_max; |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 774 | else { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 775 | if (cfg->host_caps & MMC_MODE_HS) { |
| 776 | if (cfg->host_caps & MMC_MODE_HS_52MHz) |
| 777 | cfg->f_max = 52000000; |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 778 | else |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 779 | cfg->f_max = 26000000; |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 780 | } else |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 781 | cfg->f_max = 20000000; |
Jonathan Solnit | a9b0556 | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 782 | } |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 783 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 784 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
John Rigby | f2f4366 | 2011-04-18 05:50:08 +0000 | [diff] [blame] | 785 | |
John Rigby | 91fcc4b | 2011-04-19 05:48:14 +0000 | [diff] [blame] | 786 | #if defined(CONFIG_OMAP34XX) |
| 787 | /* |
| 788 | * Silicon revs 2.1 and older do not support multiblock transfers. |
| 789 | */ |
| 790 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 791 | cfg->b_max = 1; |
John Rigby | 91fcc4b | 2011-04-19 05:48:14 +0000 | [diff] [blame] | 792 | #endif |
Jean-Jacques Hiblot | d58ef8e | 2017-03-22 16:00:31 +0100 | [diff] [blame] | 793 | mmc = mmc_create(cfg, priv); |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 794 | if (mmc == NULL) |
| 795 | return -1; |
Sukumar Ghorai | c53f5e5 | 2010-09-18 20:32:33 -0700 | [diff] [blame] | 796 | |
| 797 | return 0; |
| 798 | } |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 799 | #else |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 800 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 801 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) |
| 802 | { |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 803 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
| 804 | struct mmc_config *cfg = &plat->cfg; |
Adam Ford | c0edb0f | 2017-04-17 08:09:37 -0500 | [diff] [blame] | 805 | struct omap2_mmc_platform_config *data = |
| 806 | (struct omap2_mmc_platform_config *)dev_get_driver_data(dev); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 807 | const void *fdt = gd->fdt_blob; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 808 | int node = dev_of_offset(dev); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 809 | int val; |
| 810 | |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 811 | plat->base_addr = map_physmem(devfdt_get_addr(dev), |
| 812 | sizeof(struct hsmmc *), |
Adam Ford | c0edb0f | 2017-04-17 08:09:37 -0500 | [diff] [blame] | 813 | MAP_NOCACHE) + data->reg_offset; |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 814 | |
| 815 | cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; |
| 816 | val = fdtdec_get_int(fdt, node, "bus-width", -1); |
| 817 | if (val < 0) { |
| 818 | printf("error: bus-width property missing\n"); |
| 819 | return -ENOENT; |
| 820 | } |
| 821 | |
| 822 | switch (val) { |
| 823 | case 0x8: |
| 824 | cfg->host_caps |= MMC_MODE_8BIT; |
| 825 | case 0x4: |
| 826 | cfg->host_caps |= MMC_MODE_4BIT; |
| 827 | break; |
| 828 | default: |
| 829 | printf("error: invalid bus-width property\n"); |
| 830 | return -ENOENT; |
| 831 | } |
| 832 | |
| 833 | cfg->f_min = 400000; |
| 834 | cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); |
| 835 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
| 836 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
| 837 | |
Sekhar Nori | 640fd70 | 2016-08-10 19:24:03 +0530 | [diff] [blame] | 838 | #ifdef OMAP_HSMMC_USE_GPIO |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 839 | plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); |
Sekhar Nori | 640fd70 | 2016-08-10 19:24:03 +0530 | [diff] [blame] | 840 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 841 | |
| 842 | return 0; |
| 843 | } |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 844 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 845 | |
Jean-Jacques Hiblot | a3c556c | 2017-03-22 16:00:34 +0100 | [diff] [blame] | 846 | #ifdef CONFIG_BLK |
| 847 | |
| 848 | static int omap_hsmmc_bind(struct udevice *dev) |
| 849 | { |
| 850 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
| 851 | |
| 852 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 853 | } |
| 854 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 855 | static int omap_hsmmc_probe(struct udevice *dev) |
| 856 | { |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 857 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 858 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 859 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
Jean-Jacques Hiblot | ae51a66 | 2017-03-22 16:00:33 +0100 | [diff] [blame] | 860 | struct mmc_config *cfg = &plat->cfg; |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 861 | struct mmc *mmc; |
| 862 | |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 863 | cfg->name = "OMAP SD/MMC"; |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 864 | priv->base_addr = plat->base_addr; |
| 865 | #ifdef OMAP_HSMMC_USE_GPIO |
| 866 | priv->cd_inverted = plat->cd_inverted; |
| 867 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 868 | |
Jean-Jacques Hiblot | a3c556c | 2017-03-22 16:00:34 +0100 | [diff] [blame] | 869 | #ifdef CONFIG_BLK |
| 870 | mmc = &plat->mmc; |
| 871 | #else |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 872 | mmc = mmc_create(cfg, priv); |
| 873 | if (mmc == NULL) |
| 874 | return -1; |
Jean-Jacques Hiblot | a3c556c | 2017-03-22 16:00:34 +0100 | [diff] [blame] | 875 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 876 | |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 877 | #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL) |
Mugunthan V N | a9a0aa7 | 2016-04-04 17:28:01 +0530 | [diff] [blame] | 878 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); |
| 879 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); |
| 880 | #endif |
| 881 | |
Simon Glass | 77ca42b | 2016-05-01 13:52:34 -0600 | [diff] [blame] | 882 | mmc->dev = dev; |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 883 | upriv->mmc = mmc; |
| 884 | |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 885 | return omap_hsmmc_init_setup(mmc); |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 886 | } |
| 887 | |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 888 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
Adam Ford | c0edb0f | 2017-04-17 08:09:37 -0500 | [diff] [blame] | 889 | static const struct omap2_mmc_platform_config omap3_mmc_pdata = { |
| 890 | .reg_offset = 0, |
| 891 | }; |
| 892 | |
| 893 | static const struct omap2_mmc_platform_config am33xx_mmc_pdata = { |
| 894 | .reg_offset = 0x100, |
| 895 | }; |
| 896 | |
| 897 | static const struct omap2_mmc_platform_config omap4_mmc_pdata = { |
| 898 | .reg_offset = 0x100, |
| 899 | }; |
| 900 | |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 901 | static const struct udevice_id omap_hsmmc_ids[] = { |
Adam Ford | c0edb0f | 2017-04-17 08:09:37 -0500 | [diff] [blame] | 902 | { |
| 903 | .compatible = "ti,omap3-hsmmc", |
| 904 | .data = (ulong)&omap3_mmc_pdata |
| 905 | }, |
| 906 | { |
| 907 | .compatible = "ti,omap4-hsmmc", |
| 908 | .data = (ulong)&omap4_mmc_pdata |
| 909 | }, |
| 910 | { |
| 911 | .compatible = "ti,am33xx-hsmmc", |
| 912 | .data = (ulong)&am33xx_mmc_pdata |
| 913 | }, |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 914 | { } |
| 915 | }; |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 916 | #endif |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 917 | |
| 918 | U_BOOT_DRIVER(omap_hsmmc) = { |
| 919 | .name = "omap_hsmmc", |
| 920 | .id = UCLASS_MMC, |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 921 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 922 | .of_match = omap_hsmmc_ids, |
| 923 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, |
Lokesh Vutla | 9a696fb | 2017-04-26 13:37:05 +0530 | [diff] [blame] | 924 | .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), |
| 925 | #endif |
Jean-Jacques Hiblot | a3c556c | 2017-03-22 16:00:34 +0100 | [diff] [blame] | 926 | #ifdef CONFIG_BLK |
| 927 | .bind = omap_hsmmc_bind, |
| 928 | #endif |
Jean-Jacques Hiblot | 8fc9d3a | 2017-04-14 19:50:02 +0200 | [diff] [blame] | 929 | .ops = &omap_hsmmc_ops, |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 930 | .probe = omap_hsmmc_probe, |
| 931 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), |
Lokesh Vutla | c38e645 | 2017-04-26 13:37:06 +0530 | [diff] [blame] | 932 | .flags = DM_FLAG_PRE_RELOC, |
Mugunthan V N | d97631a | 2015-09-28 12:56:30 +0530 | [diff] [blame] | 933 | }; |
| 934 | #endif |