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wdenk4e112c12003-06-03 23:54:09 +00001/*******************************************************************************
2
wdenk57b2d802003-06-27 21:31:46 +00003
wdenk4e112c12003-06-03 23:54:09 +00004 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Roy Zang181119b2011-01-21 11:29:38 +08005 Copyright 2011 Freescale Semiconductor, Inc.
wdenk57b2d802003-06-27 21:31:46 +00006
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk57b2d802003-06-27 21:31:46 +00008
wdenk4e112c12003-06-03 23:54:09 +00009 Contact Information:
10 Linux NICS <linux.nics@intel.com>
11 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
12
13*******************************************************************************/
14
15/* e1000_hw.h
16 * Structures, enums, and macros for the MAC
17 */
18
19#ifndef _E1000_HW_H_
20#define _E1000_HW_H_
21
Kyle Moffett64b94dd2011-10-18 11:05:29 +000022#include <linux/list.h>
wdenk4e112c12003-06-03 23:54:09 +000023#include <malloc.h>
24#include <net.h>
Simon Glass9f86b382015-08-19 09:33:40 -060025/* Avoids a compile error since struct eth_device is not defined */
26#ifndef CONFIG_DM_ETH
Ben Warren050019d2008-08-31 10:44:19 -070027#include <netdev.h>
Simon Glass9f86b382015-08-19 09:33:40 -060028#endif
wdenk4e112c12003-06-03 23:54:09 +000029#include <asm/io.h>
30#include <pci.h>
31
Kyle Moffett64b94dd2011-10-18 11:05:29 +000032#ifdef CONFIG_E1000_SPI
33#include <spi.h>
34#endif
35
Kyle Moffett7b698d52011-10-18 11:05:26 +000036#define E1000_ERR(NIC, fmt, args...) \
37 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
wdenk4e112c12003-06-03 23:54:09 +000038
39#ifdef E1000_DEBUG
Kyle Moffett7b698d52011-10-18 11:05:26 +000040#define E1000_DBG(NIC, fmt, args...) \
41 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
42#define DEBUGOUT(fmt, args...) printf(fmt ,##args)
43#define DEBUGFUNC() printf("%s\n", __func__);
wdenk4e112c12003-06-03 23:54:09 +000044#else
Kyle Moffett7b698d52011-10-18 11:05:26 +000045#define E1000_DBG(HW, args...) do { } while (0)
46#define DEBUGFUNC() do { } while (0)
47#define DEBUGOUT(fmt, args...) do { } while (0)
wdenk4e112c12003-06-03 23:54:09 +000048#endif
49
Kyle Moffett142cbf82011-10-18 11:05:28 +000050/* I/O wrapper functions */
51#define E1000_WRITE_REG(a, reg, value) \
Wolfgang Denk15690332011-10-28 07:37:04 +020052 writel((value), ((a)->hw_addr + E1000_##reg))
Kyle Moffett142cbf82011-10-18 11:05:28 +000053#define E1000_READ_REG(a, reg) \
Wolfgang Denk15690332011-10-28 07:37:04 +020054 readl((a)->hw_addr + E1000_##reg)
Kyle Moffett142cbf82011-10-18 11:05:28 +000055#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
Wolfgang Denk15690332011-10-28 07:37:04 +020056 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
Kyle Moffett142cbf82011-10-18 11:05:28 +000057#define E1000_READ_REG_ARRAY(a, reg, offset) \
Wolfgang Denk15690332011-10-28 07:37:04 +020058 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
Kyle Moffett142cbf82011-10-18 11:05:28 +000059#define E1000_WRITE_FLUSH(a) \
Wolfgang Denk15690332011-10-28 07:37:04 +020060 do { E1000_READ_REG(a, STATUS); } while (0)
Kyle Moffett142cbf82011-10-18 11:05:28 +000061
wdenk4e112c12003-06-03 23:54:09 +000062/* Forward declarations of structures used by the shared code */
63struct e1000_hw;
64struct e1000_hw_stats;
65
Kyle Moffett142cbf82011-10-18 11:05:28 +000066/* Internal E1000 helper functions */
Kyle Moffett64b94dd2011-10-18 11:05:29 +000067struct e1000_hw *e1000_find_card(unsigned int cardnum);
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +020068
69#ifndef CONFIG_E1000_NO_NVM
Kyle Moffett142cbf82011-10-18 11:05:28 +000070int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
71void e1000_standby_eeprom(struct e1000_hw *hw);
72void e1000_release_eeprom(struct e1000_hw *hw);
73void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
74void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +020075#endif
Kyle Moffett142cbf82011-10-18 11:05:28 +000076
Kyle Moffett64b94dd2011-10-18 11:05:29 +000077#ifdef CONFIG_E1000_SPI
78int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
79 int argc, char * const argv[]);
80#endif
81
wdenk4e112c12003-06-03 23:54:09 +000082/* Enumerated types specific to the e1000 hardware */
83/* Media Access Controlers */
84typedef enum {
85 e1000_undefined = 0,
86 e1000_82542_rev2_0,
87 e1000_82542_rev2_1,
88 e1000_82543,
89 e1000_82544,
90 e1000_82540,
91 e1000_82545,
Roy Zang28f7a052009-07-31 13:34:02 +080092 e1000_82545_rev_3,
wdenk4e112c12003-06-03 23:54:09 +000093 e1000_82546,
Roy Zang28f7a052009-07-31 13:34:02 +080094 e1000_82546_rev_3,
Andre Schwarz68c2a302008-03-06 16:45:44 +010095 e1000_82541,
96 e1000_82541_rev_2,
Roy Zang28f7a052009-07-31 13:34:02 +080097 e1000_82547,
98 e1000_82547_rev_2,
99 e1000_82571,
100 e1000_82572,
101 e1000_82573,
Roy Zang181119b2011-01-21 11:29:38 +0800102 e1000_82574,
Roy Zang28f7a052009-07-31 13:34:02 +0800103 e1000_80003es2lan,
104 e1000_ich8lan,
Marek Vasut74a13c22014-08-08 07:41:39 -0700105 e1000_igb,
wdenk4e112c12003-06-03 23:54:09 +0000106 e1000_num_macs
107} e1000_mac_type;
108
109/* Media Types */
110typedef enum {
111 e1000_media_type_copper = 0,
112 e1000_media_type_fiber = 1,
Roy Zang28f7a052009-07-31 13:34:02 +0800113 e1000_media_type_internal_serdes = 2,
wdenk4e112c12003-06-03 23:54:09 +0000114 e1000_num_media_types
115} e1000_media_type;
116
117typedef enum {
Roy Zang28f7a052009-07-31 13:34:02 +0800118 e1000_eeprom_uninitialized = 0,
119 e1000_eeprom_spi,
120 e1000_eeprom_microwire,
121 e1000_eeprom_flash,
122 e1000_eeprom_ich8,
123 e1000_eeprom_none, /* No NVM support */
Marek Vasut74a13c22014-08-08 07:41:39 -0700124 e1000_eeprom_invm,
Roy Zang28f7a052009-07-31 13:34:02 +0800125 e1000_num_eeprom_types
126} e1000_eeprom_type;
127
128typedef enum {
wdenk4e112c12003-06-03 23:54:09 +0000129 e1000_10_half = 0,
130 e1000_10_full = 1,
131 e1000_100_half = 2,
132 e1000_100_full = 3
133} e1000_speed_duplex_type;
134
wdenk4e112c12003-06-03 23:54:09 +0000135/* Flow Control Settings */
136typedef enum {
137 e1000_fc_none = 0,
138 e1000_fc_rx_pause = 1,
139 e1000_fc_tx_pause = 2,
140 e1000_fc_full = 3,
141 e1000_fc_default = 0xFF
142} e1000_fc_type;
143
144/* PCI bus types */
145typedef enum {
146 e1000_bus_type_unknown = 0,
147 e1000_bus_type_pci,
Roy Zang28f7a052009-07-31 13:34:02 +0800148 e1000_bus_type_pcix,
149 e1000_bus_type_pci_express,
150 e1000_bus_type_reserved
wdenk4e112c12003-06-03 23:54:09 +0000151} e1000_bus_type;
152
153/* PCI bus speeds */
154typedef enum {
155 e1000_bus_speed_unknown = 0,
156 e1000_bus_speed_33,
157 e1000_bus_speed_66,
158 e1000_bus_speed_100,
159 e1000_bus_speed_133,
160 e1000_bus_speed_reserved
161} e1000_bus_speed;
162
163/* PCI bus widths */
164typedef enum {
165 e1000_bus_width_unknown = 0,
166 e1000_bus_width_32,
167 e1000_bus_width_64
168} e1000_bus_width;
169
170/* PHY status info structure and supporting enums */
171typedef enum {
172 e1000_cable_length_50 = 0,
173 e1000_cable_length_50_80,
174 e1000_cable_length_80_110,
175 e1000_cable_length_110_140,
176 e1000_cable_length_140,
177 e1000_cable_length_undefined = 0xFF
178} e1000_cable_length;
179
180typedef enum {
181 e1000_10bt_ext_dist_enable_normal = 0,
182 e1000_10bt_ext_dist_enable_lower,
183 e1000_10bt_ext_dist_enable_undefined = 0xFF
184} e1000_10bt_ext_dist_enable;
185
186typedef enum {
187 e1000_rev_polarity_normal = 0,
188 e1000_rev_polarity_reversed,
189 e1000_rev_polarity_undefined = 0xFF
190} e1000_rev_polarity;
191
192typedef enum {
193 e1000_polarity_reversal_enabled = 0,
194 e1000_polarity_reversal_disabled,
195 e1000_polarity_reversal_undefined = 0xFF
196} e1000_polarity_reversal;
197
198typedef enum {
199 e1000_auto_x_mode_manual_mdi = 0,
200 e1000_auto_x_mode_manual_mdix,
201 e1000_auto_x_mode_auto1,
202 e1000_auto_x_mode_auto2,
203 e1000_auto_x_mode_undefined = 0xFF
204} e1000_auto_x_mode;
205
206typedef enum {
207 e1000_1000t_rx_status_not_ok = 0,
208 e1000_1000t_rx_status_ok,
209 e1000_1000t_rx_status_undefined = 0xFF
210} e1000_1000t_rx_status;
211
Andre Schwarz68c2a302008-03-06 16:45:44 +0100212typedef enum {
Roy Zang28f7a052009-07-31 13:34:02 +0800213 e1000_phy_m88 = 0,
214 e1000_phy_igp,
215 e1000_phy_igp_2,
216 e1000_phy_gg82563,
217 e1000_phy_igp_3,
218 e1000_phy_ife,
Marek Vasut74a13c22014-08-08 07:41:39 -0700219 e1000_phy_igb,
Roy Zang181119b2011-01-21 11:29:38 +0800220 e1000_phy_bm,
Roy Zang28f7a052009-07-31 13:34:02 +0800221 e1000_phy_undefined = 0xFF
Andre Schwarz68c2a302008-03-06 16:45:44 +0100222} e1000_phy_type;
223
wdenk4e112c12003-06-03 23:54:09 +0000224struct e1000_phy_info {
225 e1000_cable_length cable_length;
226 e1000_10bt_ext_dist_enable extended_10bt_distance;
227 e1000_rev_polarity cable_polarity;
228 e1000_polarity_reversal polarity_correction;
229 e1000_auto_x_mode mdix_mode;
230 e1000_1000t_rx_status local_rx;
231 e1000_1000t_rx_status remote_rx;
232};
233
234struct e1000_phy_stats {
235 uint32_t idle_errors;
236 uint32_t receive_errors;
237};
238
239/* Error Codes */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200240#define E1000_SUCCESS 0
241#define E1000_ERR_EEPROM 1
242#define E1000_ERR_PHY 2
243#define E1000_ERR_CONFIG 3
244#define E1000_ERR_PARAM 4
245#define E1000_ERR_MAC_TYPE 5
246#define E1000_ERR_PHY_TYPE 6
247#define E1000_ERR_NOLINK 7
248#define E1000_ERR_TIMEOUT 8
249#define E1000_ERR_RESET 9
250#define E1000_ERR_MASTER_REQUESTS_PENDING 10
251#define E1000_ERR_HOST_INTERFACE_COMMAND 11
252#define E1000_BLK_PHY_RESET 12
Roy Zang28f7a052009-07-31 13:34:02 +0800253#define E1000_ERR_SWFW_SYNC 13
wdenk4e112c12003-06-03 23:54:09 +0000254
255/* PCI Device IDs */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200256#define E1000_DEV_ID_82542 0x1000
wdenk4e112c12003-06-03 23:54:09 +0000257#define E1000_DEV_ID_82543GC_FIBER 0x1001
258#define E1000_DEV_ID_82543GC_COPPER 0x1004
259#define E1000_DEV_ID_82544EI_COPPER 0x1008
260#define E1000_DEV_ID_82544EI_FIBER 0x1009
261#define E1000_DEV_ID_82544GC_COPPER 0x100C
262#define E1000_DEV_ID_82544GC_LOM 0x100D
Wolfgang Denka1be4762008-05-20 16:00:29 +0200263#define E1000_DEV_ID_82540EM 0x100E
Roy Zang28f7a052009-07-31 13:34:02 +0800264#define E1000_DEV_ID_82540EM_LOM 0x1015
265#define E1000_DEV_ID_82540EP_LOM 0x1016
266#define E1000_DEV_ID_82540EP 0x1017
267#define E1000_DEV_ID_82540EP_LP 0x101E
268#define E1000_DEV_ID_82545EM_COPPER 0x100F
269#define E1000_DEV_ID_82545EM_FIBER 0x1011
270#define E1000_DEV_ID_82545GM_COPPER 0x1026
271#define E1000_DEV_ID_82545GM_FIBER 0x1027
272#define E1000_DEV_ID_82545GM_SERDES 0x1028
273#define E1000_DEV_ID_82546EB_COPPER 0x1010
274#define E1000_DEV_ID_82546EB_FIBER 0x1012
275#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
276#define E1000_DEV_ID_82541EI 0x1013
277#define E1000_DEV_ID_82541EI_MOBILE 0x1018
278#define E1000_DEV_ID_82541ER_LOM 0x1014
279#define E1000_DEV_ID_82541ER 0x1078
280#define E1000_DEV_ID_82547GI 0x1075
281#define E1000_DEV_ID_82541GI 0x1076
282#define E1000_DEV_ID_82541GI_MOBILE 0x1077
283#define E1000_DEV_ID_82541GI_LF 0x107C
284#define E1000_DEV_ID_82546GB_COPPER 0x1079
285#define E1000_DEV_ID_82546GB_FIBER 0x107A
286#define E1000_DEV_ID_82546GB_SERDES 0x107B
287#define E1000_DEV_ID_82546GB_PCIE 0x108A
288#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
289#define E1000_DEV_ID_82547EI 0x1019
290#define E1000_DEV_ID_82547EI_MOBILE 0x101A
291#define E1000_DEV_ID_82571EB_COPPER 0x105E
292#define E1000_DEV_ID_82571EB_FIBER 0x105F
293#define E1000_DEV_ID_82571EB_SERDES 0x1060
294#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
295#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
296#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
297#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
298#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
299#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
300#define E1000_DEV_ID_82572EI_COPPER 0x107D
301#define E1000_DEV_ID_82572EI_FIBER 0x107E
302#define E1000_DEV_ID_82572EI_SERDES 0x107F
303#define E1000_DEV_ID_82572EI 0x10B9
304#define E1000_DEV_ID_82573E 0x108B
305#define E1000_DEV_ID_82573E_IAMT 0x108C
306#define E1000_DEV_ID_82573L 0x109A
Roy Zang181119b2011-01-21 11:29:38 +0800307#define E1000_DEV_ID_82574L 0x10D3
Roy Zang28f7a052009-07-31 13:34:02 +0800308#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
309#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
310#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
311#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
312#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
313
314#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
315#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
316#define E1000_DEV_ID_ICH8_IGP_C 0x104B
317#define E1000_DEV_ID_ICH8_IFE 0x104C
318#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
319#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
320#define E1000_DEV_ID_ICH8_IGP_M 0x104D
321
322#define IGP03E1000_E_PHY_ID 0x02A80390
323#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
324#define IFE_PLUS_E_PHY_ID 0x02A80320
325#define IFE_C_E_PHY_ID 0x02A80310
326
327#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
328 Control and Address */
329#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
330 control register */
York Sun4a598092013-04-01 11:29:11 -0700331#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false
Roy Zang28f7a052009-07-31 13:34:02 +0800332 Carrier Counter */
333#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
334 Counter */
335#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
336 Frame Counter */
337#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
338 Counter */
339#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
340 Premature End Of Frame
341 Error Counter */
342#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
343 Frame Error Counter */
344#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
345 Detect Counter */
346#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
347 Status */
348#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
349 LED configuration */
350#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
351#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
352 (HWI) */
353
354#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
355 reduced power down */
356#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
357 state of 100BASE-TX */
358#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
359 state of 10BASE-T */
360#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
361 polarity */
362#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
363 address */
364#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
365 result 1=100Mbs, 0=10Mbs */
366#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
367 duplex result 1=Full, 0=Half */
368#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
369
370#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
371 disabled */
372#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
373 0=Normal */
374#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
375 Disabled, 0=Enabled */
376#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
377 0=Normal Jabber Operation */
378#define IFE_PSC_FORCE_POLARITY_SHIFT 5
379#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
380
381#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
382 feature, default 0=disabled */
383#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
384 0=force MDI */
385#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
386#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
387 is completed */
388#define IFE_PMC_MDIX_MODE_SHIFT 6
389#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
390
391#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
392 feature */
393#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
394 0=failed */
395#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
396 on the wire */
397#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
398#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
399#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
400 type of problem on the line */
401#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
402 the cable problem, in 80cm granularity */
403#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
404#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
405#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
406 off */
407#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
408
409
Paul Gortmaker7d13b8d2008-07-09 17:50:45 -0400410#define NUM_DEV_IDS 16
wdenk4e112c12003-06-03 23:54:09 +0000411
412#define NODE_ADDRESS_SIZE 6
413#define ETH_LENGTH_OF_ADDRESS 6
414
415/* MAC decode size is 128K - This is the size of BAR0 */
416#define MAC_DECODE_SIZE (128 * 1024)
417
418#define E1000_82542_2_0_REV_ID 2
419#define E1000_82542_2_1_REV_ID 3
Roy Zang28f7a052009-07-31 13:34:02 +0800420#define E1000_REVISION_0 0
421#define E1000_REVISION_1 1
422#define E1000_REVISION_2 2
423#define E1000_REVISION_3 3
wdenk4e112c12003-06-03 23:54:09 +0000424
425#define SPEED_10 10
426#define SPEED_100 100
427#define SPEED_1000 1000
428#define HALF_DUPLEX 1
429#define FULL_DUPLEX 2
430
431/* The sizes (in bytes) of a ethernet packet */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200432#define ENET_HEADER_SIZE 14
wdenk4e112c12003-06-03 23:54:09 +0000433#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
434#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
wdenk4e112c12003-06-03 23:54:09 +0000435#define MAXIMUM_ETHERNET_PACKET_SIZE \
Bin Mengb1a5e1f2015-03-20 17:12:18 +0800436 (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
wdenk4e112c12003-06-03 23:54:09 +0000437#define MINIMUM_ETHERNET_PACKET_SIZE \
Bin Mengb1a5e1f2015-03-20 17:12:18 +0800438 (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
439#define CRC_LENGTH ETH_FCS_LEN
Wolfgang Denka1be4762008-05-20 16:00:29 +0200440#define MAX_JUMBO_FRAME_SIZE 0x3F00
wdenk4e112c12003-06-03 23:54:09 +0000441
442/* 802.1q VLAN Packet Sizes */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200443#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
wdenk4e112c12003-06-03 23:54:09 +0000444
445/* Ethertype field values */
446#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200447#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
448#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
wdenk4e112c12003-06-03 23:54:09 +0000449
450/* Packet Header defines */
451#define IP_PROTOCOL_TCP 6
452#define IP_PROTOCOL_UDP 0x11
453
454/* This defines the bits that are set in the Interrupt Mask
455 * Set/Read Register. Each bit is documented below:
456 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
wdenk57b2d802003-06-27 21:31:46 +0000457 * o RXSEQ = Receive Sequence Error
wdenk4e112c12003-06-03 23:54:09 +0000458 */
459#define POLL_IMS_ENABLE_MASK ( \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200460 E1000_IMS_RXDMT0 | \
wdenk4e112c12003-06-03 23:54:09 +0000461 E1000_IMS_RXSEQ)
462
463/* This defines the bits that are set in the Interrupt Mask
464 * Set/Read Register. Each bit is documented below:
465 * o RXT0 = Receiver Timer Interrupt (ring 0)
466 * o TXDW = Transmit Descriptor Written Back
467 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
468 * o RXSEQ = Receive Sequence Error
469 * o LSC = Link Status Change
470 */
471#define IMS_ENABLE_MASK ( \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200472 E1000_IMS_RXT0 | \
473 E1000_IMS_TXDW | \
474 E1000_IMS_RXDMT0 | \
475 E1000_IMS_RXSEQ | \
wdenk4e112c12003-06-03 23:54:09 +0000476 E1000_IMS_LSC)
477
478/* The number of high/low register pairs in the RAR. The RAR (Receive Address
479 * Registers) holds the directed and multicast addresses that we monitor. We
480 * reserve one of these spots for our directed address, allowing us room for
wdenk57b2d802003-06-27 21:31:46 +0000481 * E1000_RAR_ENTRIES - 1 multicast addresses.
wdenk4e112c12003-06-03 23:54:09 +0000482 */
483#define E1000_RAR_ENTRIES 16
484
485#define MIN_NUMBER_OF_DESCRIPTORS 8
486#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
487
488/* Receive Descriptor */
489struct e1000_rx_desc {
490 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
491 uint16_t length; /* Length of data DMAed into data buffer */
492 uint16_t csum; /* Packet checksum */
493 uint8_t status; /* Descriptor status */
494 uint8_t errors; /* Descriptor Errors */
495 uint16_t special;
496};
497
498/* Receive Decriptor bit definitions */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200499#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
500#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
501#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
502#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
503#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
504#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
505#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
506#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
507#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
508#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
509#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
510#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
511#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
512#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
wdenk4e112c12003-06-03 23:54:09 +0000513#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200514#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
wdenk4e112c12003-06-03 23:54:09 +0000515#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200516#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
wdenk4e112c12003-06-03 23:54:09 +0000517#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
518
519/* mask to determine if packets should be dropped due to frame errors */
520#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200521 E1000_RXD_ERR_CE | \
522 E1000_RXD_ERR_SE | \
523 E1000_RXD_ERR_SEQ | \
524 E1000_RXD_ERR_CXE | \
wdenk4e112c12003-06-03 23:54:09 +0000525 E1000_RXD_ERR_RXE)
526
527/* Transmit Descriptor */
528struct e1000_tx_desc {
529 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
530 union {
531 uint32_t data;
532 struct {
533 uint16_t length; /* Data buffer length */
534 uint8_t cso; /* Checksum offset */
535 uint8_t cmd; /* Descriptor control */
536 } flags;
537 } lower;
538 union {
539 uint32_t data;
540 struct {
541 uint8_t status; /* Descriptor status */
542 uint8_t css; /* Checksum start */
543 uint16_t special;
544 } fields;
545 } upper;
546};
547
548/* Transmit Descriptor bit definitions */
549#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
550#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
551#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
552#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
553#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
554#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
555#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
556#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
557#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
558#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
559#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
560#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
561#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
562#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
563#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
564#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
565#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
566#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
567#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
568#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
569
570/* Offload Context Descriptor */
571struct e1000_context_desc {
572 union {
573 uint32_t ip_config;
574 struct {
575 uint8_t ipcss; /* IP checksum start */
576 uint8_t ipcso; /* IP checksum offset */
577 uint16_t ipcse; /* IP checksum end */
578 } ip_fields;
579 } lower_setup;
580 union {
581 uint32_t tcp_config;
582 struct {
583 uint8_t tucss; /* TCP checksum start */
584 uint8_t tucso; /* TCP checksum offset */
585 uint16_t tucse; /* TCP checksum end */
586 } tcp_fields;
587 } upper_setup;
588 uint32_t cmd_and_length; /* */
589 union {
590 uint32_t data;
591 struct {
592 uint8_t status; /* Descriptor status */
593 uint8_t hdr_len; /* Header length */
594 uint16_t mss; /* Maximum segment size */
595 } fields;
596 } tcp_seg_setup;
597};
598
599/* Offload data descriptor */
600struct e1000_data_desc {
601 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
602 union {
603 uint32_t data;
604 struct {
605 uint16_t length; /* Data buffer length */
606 uint8_t typ_len_ext; /* */
607 uint8_t cmd; /* */
608 } flags;
609 } lower;
610 union {
611 uint32_t data;
612 struct {
613 uint8_t status; /* Descriptor status */
614 uint8_t popts; /* Packet Options */
615 uint16_t special; /* */
616 } fields;
617 } upper;
618};
619
620/* Filters */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200621#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
622#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
wdenk4e112c12003-06-03 23:54:09 +0000623#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
624
625/* Receive Address Register */
626struct e1000_rar {
627 volatile uint32_t low; /* receive address low */
628 volatile uint32_t high; /* receive address high */
629};
630
631/* The number of entries in the Multicast Table Array (MTA). */
632#define E1000_NUM_MTA_REGISTERS 128
633
634/* IPv4 Address Table Entry */
635struct e1000_ipv4_at_entry {
636 volatile uint32_t ipv4_addr; /* IP Address (RW) */
637 volatile uint32_t reserved;
638};
639
640/* Four wakeup IP addresses are supported */
641#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
Wolfgang Denka1be4762008-05-20 16:00:29 +0200642#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
643#define E1000_IP6AT_SIZE 1
wdenk4e112c12003-06-03 23:54:09 +0000644
645/* IPv6 Address Table Entry */
646struct e1000_ipv6_at_entry {
647 volatile uint8_t ipv6_addr[16];
648};
649
650/* Flexible Filter Length Table Entry */
651struct e1000_fflt_entry {
652 volatile uint32_t length; /* Flexible Filter Length (RW) */
653 volatile uint32_t reserved;
654};
655
656/* Flexible Filter Mask Table Entry */
657struct e1000_ffmt_entry {
658 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
659 volatile uint32_t reserved;
660};
661
662/* Flexible Filter Value Table Entry */
663struct e1000_ffvt_entry {
664 volatile uint32_t value; /* Flexible Filter Value (RW) */
665 volatile uint32_t reserved;
666};
667
668/* Four Flexible Filters are supported */
669#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
670
671/* Each Flexible Filter is at most 128 (0x80) bytes in length */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200672#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
wdenk4e112c12003-06-03 23:54:09 +0000673
674#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
675#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
676#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
677
678/* Register Set. (82543, 82544)
679 *
680 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
wdenk57b2d802003-06-27 21:31:46 +0000681 * These registers are physically located on the NIC, but are mapped into the
wdenk4e112c12003-06-03 23:54:09 +0000682 * host memory address space.
683 *
684 * RW - register is both readable and writable
685 * RO - register is read only
686 * WO - register is write only
687 * R/clr - register is read only and is cleared when read
688 * A - register array
689 */
690#define E1000_CTRL 0x00000 /* Device Control - RW */
691#define E1000_STATUS 0x00008 /* Device Status - RO */
692#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
Marek Vasut74a13c22014-08-08 07:41:39 -0700693#define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */
wdenk4e112c12003-06-03 23:54:09 +0000694#define E1000_EERD 0x00014 /* EEPROM Read - RW */
Marek Vasut74a13c22014-08-08 07:41:39 -0700695#define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */
wdenk4e112c12003-06-03 23:54:09 +0000696#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
697#define E1000_MDIC 0x00020 /* MDI Control - RW */
698#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
699#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
700#define E1000_FCT 0x00030 /* Flow Control Type - RW */
701#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
702#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
703#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
704#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
705#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
706#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
Marek Vasut74a13c22014-08-08 07:41:39 -0700707#define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */
wdenk4e112c12003-06-03 23:54:09 +0000708#define E1000_RCTL 0x00100 /* RX Control - RW */
709#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
710#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
711#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
712#define E1000_TCTL 0x00400 /* TX Control - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800713#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
wdenk4e112c12003-06-03 23:54:09 +0000714#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
715#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
716#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
717#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800718#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
719#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
720#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
Marek Vasut74a13c22014-08-08 07:41:39 -0700721#define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */
Roy Zang28f7a052009-07-31 13:34:02 +0800722#define FEXTNVM_SW_CONFIG 0x0001
wdenk4e112c12003-06-03 23:54:09 +0000723#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800724#define E1000_PBS 0x01008 /* Packet Buffer Size */
725#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
Marek Vasut74a13c22014-08-08 07:41:39 -0700726#define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */
Roy Zang28f7a052009-07-31 13:34:02 +0800727#define E1000_FLASH_UPDATES 1000
728#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
729#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
730#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
Marek Vasut74a13c22014-08-08 07:41:39 -0700731#define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800732#define E1000_FLSWCTL 0x01030 /* FLASH control register */
733#define E1000_FLSWDATA 0x01034 /* FLASH data register */
734#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
735#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
736#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
wdenk4e112c12003-06-03 23:54:09 +0000737#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
738#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
739#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
740#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
741#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
742#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
743#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
744#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
745#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
746#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
747#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
748#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800749#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
750#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
751#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
752#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
753#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
wdenk4e112c12003-06-03 23:54:09 +0000754#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
755#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
756#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
757#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
758#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
759#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
760#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
761#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
762#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
Roy Zang28f7a052009-07-31 13:34:02 +0800763#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
764#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
765#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
766#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
767#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
768#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
769#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
770#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
wdenk4e112c12003-06-03 23:54:09 +0000771#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
772#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
773#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
774#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
775#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
776#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
777#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
778#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
779#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
780#define E1000_COLC 0x04028 /* Collision Count - R/clr */
781#define E1000_DC 0x04030 /* Defer Count - R/clr */
782#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
783#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
784#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
785#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
786#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
787#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
788#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
789#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
790#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
791#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
792#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
793#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
794#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
795#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
796#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
797#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
798#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
799#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
800#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
801#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
802#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
803#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
804#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
805#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
806#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
807#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
808#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
809#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
810#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
811#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
812#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
813#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
814#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
815#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
816#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
817#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
818#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
819#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
820#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
821#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
822#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
823#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
824#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
825#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
826#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
827#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
828#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
829#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
830#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
831#define E1000_RA 0x05400 /* Receive Address - RW Array */
832#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
833#define E1000_WUC 0x05800 /* Wakeup Control - RW */
834#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
835#define E1000_WUS 0x05810 /* Wakeup Status - RO */
836#define E1000_MANC 0x05820 /* Management Control - RW */
837#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
838#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
839#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
840#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
841#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
842#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
843#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
844#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
845
846/* Register Set (82542)
847 *
848 * Some of the 82542 registers are located at different offsets than they are
849 * in more current versions of the 8254x. Despite the difference in location,
850 * the registers function in the same manner.
851 */
852#define E1000_82542_CTRL E1000_CTRL
853#define E1000_82542_STATUS E1000_STATUS
854#define E1000_82542_EECD E1000_EECD
855#define E1000_82542_EERD E1000_EERD
856#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
857#define E1000_82542_MDIC E1000_MDIC
858#define E1000_82542_FCAL E1000_FCAL
859#define E1000_82542_FCAH E1000_FCAH
860#define E1000_82542_FCT E1000_FCT
861#define E1000_82542_VET E1000_VET
Wolfgang Denka1be4762008-05-20 16:00:29 +0200862#define E1000_82542_RA 0x00040
wdenk4e112c12003-06-03 23:54:09 +0000863#define E1000_82542_ICR E1000_ICR
864#define E1000_82542_ITR E1000_ITR
865#define E1000_82542_ICS E1000_ICS
866#define E1000_82542_IMS E1000_IMS
867#define E1000_82542_IMC E1000_IMC
868#define E1000_82542_RCTL E1000_RCTL
869#define E1000_82542_RDTR 0x00108
870#define E1000_82542_RDBAL 0x00110
871#define E1000_82542_RDBAH 0x00114
872#define E1000_82542_RDLEN 0x00118
873#define E1000_82542_RDH 0x00120
874#define E1000_82542_RDT 0x00128
875#define E1000_82542_FCRTH 0x00160
876#define E1000_82542_FCRTL 0x00168
877#define E1000_82542_FCTTV E1000_FCTTV
878#define E1000_82542_TXCW E1000_TXCW
879#define E1000_82542_RXCW E1000_RXCW
880#define E1000_82542_MTA 0x00200
881#define E1000_82542_TCTL E1000_TCTL
882#define E1000_82542_TIPG E1000_TIPG
883#define E1000_82542_TDBAL 0x00420
884#define E1000_82542_TDBAH 0x00424
885#define E1000_82542_TDLEN 0x00428
886#define E1000_82542_TDH 0x00430
887#define E1000_82542_TDT 0x00438
888#define E1000_82542_TIDV 0x00440
889#define E1000_82542_TBT E1000_TBT
890#define E1000_82542_AIT E1000_AIT
891#define E1000_82542_VFTA 0x00600
892#define E1000_82542_LEDCTL E1000_LEDCTL
893#define E1000_82542_PBA E1000_PBA
894#define E1000_82542_RXDCTL E1000_RXDCTL
895#define E1000_82542_RADV E1000_RADV
896#define E1000_82542_RSRPD E1000_RSRPD
897#define E1000_82542_TXDMAC E1000_TXDMAC
898#define E1000_82542_TXDCTL E1000_TXDCTL
899#define E1000_82542_TADV E1000_TADV
900#define E1000_82542_TSPMT E1000_TSPMT
901#define E1000_82542_CRCERRS E1000_CRCERRS
902#define E1000_82542_ALGNERRC E1000_ALGNERRC
903#define E1000_82542_SYMERRS E1000_SYMERRS
904#define E1000_82542_RXERRC E1000_RXERRC
905#define E1000_82542_MPC E1000_MPC
906#define E1000_82542_SCC E1000_SCC
907#define E1000_82542_ECOL E1000_ECOL
908#define E1000_82542_MCC E1000_MCC
909#define E1000_82542_LATECOL E1000_LATECOL
910#define E1000_82542_COLC E1000_COLC
Wolfgang Denka1be4762008-05-20 16:00:29 +0200911#define E1000_82542_DC E1000_DC
wdenk4e112c12003-06-03 23:54:09 +0000912#define E1000_82542_TNCRS E1000_TNCRS
913#define E1000_82542_SEC E1000_SEC
914#define E1000_82542_CEXTERR E1000_CEXTERR
915#define E1000_82542_RLEC E1000_RLEC
916#define E1000_82542_XONRXC E1000_XONRXC
917#define E1000_82542_XONTXC E1000_XONTXC
918#define E1000_82542_XOFFRXC E1000_XOFFRXC
919#define E1000_82542_XOFFTXC E1000_XOFFTXC
920#define E1000_82542_FCRUC E1000_FCRUC
921#define E1000_82542_PRC64 E1000_PRC64
922#define E1000_82542_PRC127 E1000_PRC127
923#define E1000_82542_PRC255 E1000_PRC255
924#define E1000_82542_PRC511 E1000_PRC511
925#define E1000_82542_PRC1023 E1000_PRC1023
926#define E1000_82542_PRC1522 E1000_PRC1522
927#define E1000_82542_GPRC E1000_GPRC
928#define E1000_82542_BPRC E1000_BPRC
929#define E1000_82542_MPRC E1000_MPRC
930#define E1000_82542_GPTC E1000_GPTC
931#define E1000_82542_GORCL E1000_GORCL
932#define E1000_82542_GORCH E1000_GORCH
933#define E1000_82542_GOTCL E1000_GOTCL
934#define E1000_82542_GOTCH E1000_GOTCH
935#define E1000_82542_RNBC E1000_RNBC
936#define E1000_82542_RUC E1000_RUC
937#define E1000_82542_RFC E1000_RFC
938#define E1000_82542_ROC E1000_ROC
939#define E1000_82542_RJC E1000_RJC
940#define E1000_82542_MGTPRC E1000_MGTPRC
941#define E1000_82542_MGTPDC E1000_MGTPDC
942#define E1000_82542_MGTPTC E1000_MGTPTC
943#define E1000_82542_TORL E1000_TORL
944#define E1000_82542_TORH E1000_TORH
945#define E1000_82542_TOTL E1000_TOTL
946#define E1000_82542_TOTH E1000_TOTH
947#define E1000_82542_TPR E1000_TPR
948#define E1000_82542_TPT E1000_TPT
949#define E1000_82542_PTC64 E1000_PTC64
950#define E1000_82542_PTC127 E1000_PTC127
951#define E1000_82542_PTC255 E1000_PTC255
952#define E1000_82542_PTC511 E1000_PTC511
953#define E1000_82542_PTC1023 E1000_PTC1023
954#define E1000_82542_PTC1522 E1000_PTC1522
955#define E1000_82542_MPTC E1000_MPTC
956#define E1000_82542_BPTC E1000_BPTC
957#define E1000_82542_TSCTC E1000_TSCTC
958#define E1000_82542_TSCTFC E1000_TSCTFC
959#define E1000_82542_RXCSUM E1000_RXCSUM
960#define E1000_82542_WUC E1000_WUC
961#define E1000_82542_WUFC E1000_WUFC
962#define E1000_82542_WUS E1000_WUS
963#define E1000_82542_MANC E1000_MANC
964#define E1000_82542_IPAV E1000_IPAV
965#define E1000_82542_IP4AT E1000_IP4AT
966#define E1000_82542_IP6AT E1000_IP6AT
967#define E1000_82542_WUPL E1000_WUPL
968#define E1000_82542_WUPM E1000_WUPM
969#define E1000_82542_FFLT E1000_FFLT
970#define E1000_82542_FFMT E1000_FFMT
971#define E1000_82542_FFVT E1000_FFVT
972
973/* Statistics counters collected by the MAC */
974struct e1000_hw_stats {
975 uint64_t crcerrs;
976 uint64_t algnerrc;
977 uint64_t symerrs;
978 uint64_t rxerrc;
979 uint64_t mpc;
980 uint64_t scc;
981 uint64_t ecol;
982 uint64_t mcc;
983 uint64_t latecol;
984 uint64_t colc;
985 uint64_t dc;
986 uint64_t tncrs;
987 uint64_t sec;
988 uint64_t cexterr;
989 uint64_t rlec;
990 uint64_t xonrxc;
991 uint64_t xontxc;
992 uint64_t xoffrxc;
993 uint64_t xofftxc;
994 uint64_t fcruc;
995 uint64_t prc64;
996 uint64_t prc127;
997 uint64_t prc255;
998 uint64_t prc511;
999 uint64_t prc1023;
1000 uint64_t prc1522;
1001 uint64_t gprc;
1002 uint64_t bprc;
1003 uint64_t mprc;
1004 uint64_t gptc;
1005 uint64_t gorcl;
1006 uint64_t gorch;
1007 uint64_t gotcl;
1008 uint64_t gotch;
1009 uint64_t rnbc;
1010 uint64_t ruc;
1011 uint64_t rfc;
1012 uint64_t roc;
1013 uint64_t rjc;
1014 uint64_t mgprc;
1015 uint64_t mgpdc;
1016 uint64_t mgptc;
1017 uint64_t torl;
1018 uint64_t torh;
1019 uint64_t totl;
1020 uint64_t toth;
1021 uint64_t tpr;
1022 uint64_t tpt;
1023 uint64_t ptc64;
1024 uint64_t ptc127;
1025 uint64_t ptc255;
1026 uint64_t ptc511;
1027 uint64_t ptc1023;
1028 uint64_t ptc1522;
1029 uint64_t mptc;
1030 uint64_t bptc;
1031 uint64_t tsctc;
1032 uint64_t tsctfc;
1033};
1034
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001035#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001036struct e1000_eeprom_info {
York Sun4a598092013-04-01 11:29:11 -07001037e1000_eeprom_type type;
1038 uint16_t word_size;
1039 uint16_t opcode_bits;
1040 uint16_t address_bits;
1041 uint16_t delay_usec;
1042 uint16_t page_size;
1043 bool use_eerd;
1044 bool use_eewr;
Roy Zang28f7a052009-07-31 13:34:02 +08001045};
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001046#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001047
1048typedef enum {
1049 e1000_smart_speed_default = 0,
1050 e1000_smart_speed_on,
1051 e1000_smart_speed_off
1052} e1000_smart_speed;
1053
1054typedef enum {
1055 e1000_dsp_config_disabled = 0,
1056 e1000_dsp_config_enabled,
1057 e1000_dsp_config_activated,
1058 e1000_dsp_config_undefined = 0xFF
1059} e1000_dsp_config;
1060
1061typedef enum {
1062 e1000_ms_hw_default = 0,
1063 e1000_ms_force_master,
1064 e1000_ms_force_slave,
1065 e1000_ms_auto
1066} e1000_ms_type;
1067
1068typedef enum {
1069 e1000_ffe_config_enabled = 0,
1070 e1000_ffe_config_active,
1071 e1000_ffe_config_blocked
1072} e1000_ffe_config;
1073
1074
wdenk4e112c12003-06-03 23:54:09 +00001075/* Structure containing variables used by the shared code (e1000_hw.c) */
1076struct e1000_hw {
Simon Glassc53abc32015-08-19 09:33:39 -06001077 const char *name;
Kyle Moffett64b94dd2011-10-18 11:05:29 +00001078 struct list_head list_node;
Simon Glass9f86b382015-08-19 09:33:40 -06001079#ifndef CONFIG_DM_ETH
Kyle Moffett7b698d52011-10-18 11:05:26 +00001080 struct eth_device *nic;
Simon Glass9f86b382015-08-19 09:33:40 -06001081#endif
Kyle Moffett64b94dd2011-10-18 11:05:29 +00001082#ifdef CONFIG_E1000_SPI
1083 struct spi_slave spi;
1084#endif
Kyle Moffett7b698d52011-10-18 11:05:26 +00001085 unsigned int cardnum;
1086
wdenk4e112c12003-06-03 23:54:09 +00001087 pci_dev_t pdev;
1088 uint8_t *hw_addr;
1089 e1000_mac_type mac_type;
Andre Schwarz68c2a302008-03-06 16:45:44 +01001090 e1000_phy_type phy_type;
1091 uint32_t phy_init_script;
Roy Zang28f7a052009-07-31 13:34:02 +08001092 uint32_t txd_cmd;
wdenk4e112c12003-06-03 23:54:09 +00001093 e1000_media_type media_type;
wdenk4e112c12003-06-03 23:54:09 +00001094 e1000_fc_type fc;
Roy Zang28f7a052009-07-31 13:34:02 +08001095 e1000_bus_type bus_type;
wdenk4e112c12003-06-03 23:54:09 +00001096#if 0
1097 e1000_bus_speed bus_speed;
1098 e1000_bus_width bus_width;
wdenk4e112c12003-06-03 23:54:09 +00001099 uint32_t io_base;
1100#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001101 uint32_t asf_firmware_present;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001102#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001103 uint32_t eeprom_semaphore_present;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001104#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001105 uint32_t swfw_sync_present;
1106 uint32_t swfwhw_semaphore_present;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001107#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001108 struct e1000_eeprom_info eeprom;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001109#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001110 e1000_ms_type master_slave;
1111 e1000_ms_type original_master_slave;
1112 e1000_ffe_config ffe_config_state;
wdenk4e112c12003-06-03 23:54:09 +00001113 uint32_t phy_id;
Roy Zang28f7a052009-07-31 13:34:02 +08001114 uint32_t phy_revision;
wdenk4e112c12003-06-03 23:54:09 +00001115 uint32_t phy_addr;
1116 uint32_t original_fc;
1117 uint32_t txcw;
1118 uint32_t autoneg_failed;
1119#if 0
1120 uint32_t max_frame_size;
1121 uint32_t min_frame_size;
1122 uint32_t mc_filter_type;
1123 uint32_t num_mc_addrs;
1124 uint32_t collision_delta;
1125 uint32_t tx_packet_delta;
1126 uint32_t ledctl_default;
1127 uint32_t ledctl_mode1;
1128 uint32_t ledctl_mode2;
1129#endif
1130 uint16_t autoneg_advertised;
1131 uint16_t pci_cmd_word;
1132 uint16_t fc_high_water;
1133 uint16_t fc_low_water;
1134 uint16_t fc_pause_time;
1135#if 0
1136 uint16_t current_ifs_val;
1137 uint16_t ifs_min_val;
1138 uint16_t ifs_max_val;
1139 uint16_t ifs_step_size;
1140 uint16_t ifs_ratio;
1141#endif
1142 uint16_t device_id;
1143 uint16_t vendor_id;
1144 uint16_t subsystem_id;
1145 uint16_t subsystem_vendor_id;
1146 uint8_t revision_id;
wdenk4e112c12003-06-03 23:54:09 +00001147 uint8_t autoneg;
1148 uint8_t mdix;
1149 uint8_t forced_speed_duplex;
1150 uint8_t wait_autoneg_complete;
1151 uint8_t dma_fairness;
wdenk4e112c12003-06-03 23:54:09 +00001152#if 0
1153 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
wdenk4e112c12003-06-03 23:54:09 +00001154#endif
York Sun4a598092013-04-01 11:29:11 -07001155 bool disable_polarity_correction;
1156 bool speed_downgraded;
1157 bool get_link_status;
1158 bool tbi_compatibility_en;
1159 bool tbi_compatibility_on;
1160 bool fc_strict_ieee;
1161 bool fc_send_xon;
1162 bool report_tx_early;
1163 bool phy_reset_disable;
1164 bool initialize_hw_bits_disable;
wdenk4e112c12003-06-03 23:54:09 +00001165#if 0
York Sun4a598092013-04-01 11:29:11 -07001166 bool adaptive_ifs;
1167 bool ifs_params_forced;
1168 bool in_ifs_mode;
wdenk4e112c12003-06-03 23:54:09 +00001169#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001170 e1000_smart_speed smart_speed;
1171 e1000_dsp_config dsp_config_state;
wdenk4e112c12003-06-03 23:54:09 +00001172};
1173
1174#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1175#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
Roy Zang28f7a052009-07-31 13:34:02 +08001176#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
1177 read/write registers */
1178#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1179#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
1180 operation */
1181#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1182#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
1183 complete */
1184#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1185#define EEPROM_RESERVED_WORD 0xFFFF
wdenk4e112c12003-06-03 23:54:09 +00001186
1187/* Register Bit Masks */
1188/* Device Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001189#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1190#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
wdenk4e112c12003-06-03 23:54:09 +00001191#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1192#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001193#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1194#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
wdenk4e112c12003-06-03 23:54:09 +00001195#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001196#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
wdenk4e112c12003-06-03 23:54:09 +00001197#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1198#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1199#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1200#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1201#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1202#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1203#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1204#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1205#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1206#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1207#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1208#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1209#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1210#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1211#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1212#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001213#define E1000_CTRL_RST 0x04000000 /* Global reset */
wdenk4e112c12003-06-03 23:54:09 +00001214#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1215#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001216#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1217#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
wdenk4e112c12003-06-03 23:54:09 +00001218#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1219
1220/* Device Status */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001221#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1222#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1223#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1224#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1225#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1226#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1227#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
wdenk4e112c12003-06-03 23:54:09 +00001228#define E1000_STATUS_SPEED_MASK 0x000000C0
Wolfgang Denka1be4762008-05-20 16:00:29 +02001229#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1230#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
wdenk4e112c12003-06-03 23:54:09 +00001231#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001232#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1233#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1234#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1235#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1236#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
wdenk4e112c12003-06-03 23:54:09 +00001237#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
Marek Vasut74a13c22014-08-08 07:41:39 -07001238#define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */
wdenk4e112c12003-06-03 23:54:09 +00001239
1240/* Constants used to intrepret the masked PCI-X bus speed. */
1241#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1242#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1243#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1244
1245/* EEPROM/Flash Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001246#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1247#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1248#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1249#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
wdenk4e112c12003-06-03 23:54:09 +00001250#define E1000_EECD_FWE_MASK 0x00000030
1251#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1252#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1253#define E1000_EECD_FWE_SHIFT 4
1254#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001255#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1256#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
wdenk4e112c12003-06-03 23:54:09 +00001257#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
Roy Zang28f7a052009-07-31 13:34:02 +08001258#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1259 * (0-small, 1-large) */
1260
1261#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1262#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1263#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1264#endif
1265#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1266#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1267#define E1000_EECD_SIZE_EX_SHIFT 11
1268#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1269#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1270#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1271#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1272#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1273#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1274#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1275#define E1000_EECD_SECVAL_SHIFT 22
1276#define E1000_STM_OPCODE 0xDB00
1277#define E1000_HICR_FW_RESET 0xC0
1278
1279#define E1000_SHADOW_RAM_WORDS 2048
1280#define E1000_ICH_NVM_SIG_WORD 0x13
1281#define E1000_ICH_NVM_SIG_MASK 0xC0
wdenk4e112c12003-06-03 23:54:09 +00001282
1283/* EEPROM Read */
1284#define E1000_EERD_START 0x00000001 /* Start Read */
1285#define E1000_EERD_DONE 0x00000010 /* Read Done */
1286#define E1000_EERD_ADDR_SHIFT 8
1287#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1288#define E1000_EERD_DATA_SHIFT 16
1289#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1290
Roy Zang28f7a052009-07-31 13:34:02 +08001291/* EEPROM Commands - Microwire */
1292#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1293#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1294#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1295#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1296#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1297
1298/* EEPROM Commands - SPI */
1299#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1300#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1301#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1302#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1303#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1304#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1305#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1306#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1307#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1308#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1309#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1310
1311/* EEPROM Size definitions */
1312#define EEPROM_WORD_SIZE_SHIFT 6
1313#define EEPROM_SIZE_SHIFT 10
1314#define EEPROM_SIZE_MASK 0x1C00
1315
1316/* EEPROM Word Offsets */
1317#define EEPROM_COMPAT 0x0003
1318#define EEPROM_ID_LED_SETTINGS 0x0004
1319#define EEPROM_VERSION 0x0005
1320#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
1321 adjustment. */
1322#define EEPROM_PHY_CLASS_WORD 0x0007
1323#define EEPROM_INIT_CONTROL1_REG 0x000A
1324#define EEPROM_INIT_CONTROL2_REG 0x000F
1325#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
1326#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1327#define EEPROM_INIT_3GIO_3 0x001A
1328#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
1329#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1330#define EEPROM_CFG 0x0012
1331#define EEPROM_FLASH_VERSION 0x0032
1332#define EEPROM_CHECKSUM_REG 0x003F
1333
1334#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
1335#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
1336
wdenk4e112c12003-06-03 23:54:09 +00001337/* Extended Device Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001338#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1339#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
wdenk4e112c12003-06-03 23:54:09 +00001340#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
Wolfgang Denka1be4762008-05-20 16:00:29 +02001341#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1342#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
Roy Zang28f7a052009-07-31 13:34:02 +08001343#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
1344 Pin 4 */
1345#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
1346 Pin 5 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001347#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
wdenk4e112c12003-06-03 23:54:09 +00001348#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001349#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
wdenk4e112c12003-06-03 23:54:09 +00001350#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001351#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
wdenk4e112c12003-06-03 23:54:09 +00001352#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1353#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1354#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001355#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
wdenk4e112c12003-06-03 23:54:09 +00001356#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001357#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
1358#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1359#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1360#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
wdenk4e112c12003-06-03 23:54:09 +00001361#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
Roy Zang28f7a052009-07-31 13:34:02 +08001362#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
wdenk4e112c12003-06-03 23:54:09 +00001363#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1364#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1365#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1366#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1367#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1368#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1369#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1370#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1371
1372/* MDI Control */
1373#define E1000_MDIC_DATA_MASK 0x0000FFFF
1374#define E1000_MDIC_REG_MASK 0x001F0000
1375#define E1000_MDIC_REG_SHIFT 16
1376#define E1000_MDIC_PHY_MASK 0x03E00000
1377#define E1000_MDIC_PHY_SHIFT 21
1378#define E1000_MDIC_OP_WRITE 0x04000000
1379#define E1000_MDIC_OP_READ 0x08000000
1380#define E1000_MDIC_READY 0x10000000
1381#define E1000_MDIC_INT_EN 0x20000000
1382#define E1000_MDIC_ERROR 0x40000000
1383
Roy Zang28f7a052009-07-31 13:34:02 +08001384#define E1000_PHY_CTRL_SPD_EN 0x00000001
1385#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1386#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1387#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1388#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1389#define E1000_PHY_CTRL_B2B_EN 0x00000080
wdenk4e112c12003-06-03 23:54:09 +00001390/* LED Control */
1391#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1392#define E1000_LEDCTL_LED0_MODE_SHIFT 0
Wolfgang Denka1be4762008-05-20 16:00:29 +02001393#define E1000_LEDCTL_LED0_IVRT 0x00000040
wdenk4e112c12003-06-03 23:54:09 +00001394#define E1000_LEDCTL_LED0_BLINK 0x00000080
1395#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1396#define E1000_LEDCTL_LED1_MODE_SHIFT 8
Wolfgang Denka1be4762008-05-20 16:00:29 +02001397#define E1000_LEDCTL_LED1_IVRT 0x00004000
wdenk4e112c12003-06-03 23:54:09 +00001398#define E1000_LEDCTL_LED1_BLINK 0x00008000
1399#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1400#define E1000_LEDCTL_LED2_MODE_SHIFT 16
Wolfgang Denka1be4762008-05-20 16:00:29 +02001401#define E1000_LEDCTL_LED2_IVRT 0x00400000
wdenk4e112c12003-06-03 23:54:09 +00001402#define E1000_LEDCTL_LED2_BLINK 0x00800000
1403#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1404#define E1000_LEDCTL_LED3_MODE_SHIFT 24
Wolfgang Denka1be4762008-05-20 16:00:29 +02001405#define E1000_LEDCTL_LED3_IVRT 0x40000000
wdenk4e112c12003-06-03 23:54:09 +00001406#define E1000_LEDCTL_LED3_BLINK 0x80000000
1407
Wolfgang Denka1be4762008-05-20 16:00:29 +02001408#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
wdenk4e112c12003-06-03 23:54:09 +00001409#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
Wolfgang Denka1be4762008-05-20 16:00:29 +02001410#define E1000_LEDCTL_MODE_LINK_UP 0x2
1411#define E1000_LEDCTL_MODE_ACTIVITY 0x3
wdenk4e112c12003-06-03 23:54:09 +00001412#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
Wolfgang Denka1be4762008-05-20 16:00:29 +02001413#define E1000_LEDCTL_MODE_LINK_10 0x5
1414#define E1000_LEDCTL_MODE_LINK_100 0x6
1415#define E1000_LEDCTL_MODE_LINK_1000 0x7
1416#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1417#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1418#define E1000_LEDCTL_MODE_COLLISION 0xA
1419#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1420#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1421#define E1000_LEDCTL_MODE_PAUSED 0xD
1422#define E1000_LEDCTL_MODE_LED_ON 0xE
1423#define E1000_LEDCTL_MODE_LED_OFF 0xF
wdenk4e112c12003-06-03 23:54:09 +00001424
1425/* Receive Address */
1426#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1427
1428/* Interrupt Cause Read */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001429#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1430#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1431#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
wdenk4e112c12003-06-03 23:54:09 +00001432#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1433#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001434#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1435#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1436#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
wdenk4e112c12003-06-03 23:54:09 +00001437#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1438#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1439#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1440#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1441#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1442#define E1000_ICR_TXD_LOW 0x00008000
Wolfgang Denka1be4762008-05-20 16:00:29 +02001443#define E1000_ICR_SRPD 0x00010000
wdenk4e112c12003-06-03 23:54:09 +00001444
1445/* Interrupt Cause Set */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001446#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1447#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1448#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
wdenk4e112c12003-06-03 23:54:09 +00001449#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1450#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001451#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1452#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1453#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
wdenk4e112c12003-06-03 23:54:09 +00001454#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1455#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1456#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1457#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1458#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1459#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
Wolfgang Denka1be4762008-05-20 16:00:29 +02001460#define E1000_ICS_SRPD E1000_ICR_SRPD
wdenk4e112c12003-06-03 23:54:09 +00001461
1462/* Interrupt Mask Set */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001463#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1464#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1465#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
wdenk4e112c12003-06-03 23:54:09 +00001466#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1467#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001468#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1469#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1470#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
wdenk4e112c12003-06-03 23:54:09 +00001471#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1472#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1473#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1474#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1475#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1476#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
Wolfgang Denka1be4762008-05-20 16:00:29 +02001477#define E1000_IMS_SRPD E1000_ICR_SRPD
wdenk4e112c12003-06-03 23:54:09 +00001478
1479/* Interrupt Mask Clear */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001480#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1481#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1482#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
wdenk4e112c12003-06-03 23:54:09 +00001483#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1484#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001485#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1486#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1487#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
wdenk4e112c12003-06-03 23:54:09 +00001488#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1489#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1490#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1491#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1492#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1493#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
Wolfgang Denka1be4762008-05-20 16:00:29 +02001494#define E1000_IMC_SRPD E1000_ICR_SRPD
wdenk4e112c12003-06-03 23:54:09 +00001495
1496/* Receive Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001497#define E1000_RCTL_RST 0x00000001 /* Software reset */
1498#define E1000_RCTL_EN 0x00000002 /* enable */
1499#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1500#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1501#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1502#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1503#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1504#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1505#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1506#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1507#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1508#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1509#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1510#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1511#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1512#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1513#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1514#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1515#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1516#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
wdenk4e112c12003-06-03 23:54:09 +00001517/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001518#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1519#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1520#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1521#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
wdenk4e112c12003-06-03 23:54:09 +00001522/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001523#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1524#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1525#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1526#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1527#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1528#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1529#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1530#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1531#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
wdenk4e112c12003-06-03 23:54:09 +00001532
Roy Zang28f7a052009-07-31 13:34:02 +08001533/* SW_W_SYNC definitions */
1534#define E1000_SWFW_EEP_SM 0x0001
1535#define E1000_SWFW_PHY0_SM 0x0002
1536#define E1000_SWFW_PHY1_SM 0x0004
1537#define E1000_SWFW_MAC_CSR_SM 0x0008
1538
wdenk4e112c12003-06-03 23:54:09 +00001539/* Receive Descriptor */
1540#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001541#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
wdenk4e112c12003-06-03 23:54:09 +00001542#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001543#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1544#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
wdenk4e112c12003-06-03 23:54:09 +00001545
1546/* Flow Control */
1547#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1548#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1549#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1550#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1551
1552/* Receive Descriptor Control */
1553#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1554#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1555#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1556#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
Ruchika Guptaed1f72f2012-04-19 02:27:11 +00001557#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
wdenk4e112c12003-06-03 23:54:09 +00001558
1559/* Transmit Descriptor Control */
Roy Zang28f7a052009-07-31 13:34:02 +08001560#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1561#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1562#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
wdenk4e112c12003-06-03 23:54:09 +00001563#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1564#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1565#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
Roy Zang28f7a052009-07-31 13:34:02 +08001566#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1567 still to be processed. */
wdenk4e112c12003-06-03 23:54:09 +00001568
1569/* Transmit Configuration Word */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001570#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1571#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
wdenk4e112c12003-06-03 23:54:09 +00001572#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1573#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1574#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001575#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1576#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1577#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1578#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1579#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
wdenk4e112c12003-06-03 23:54:09 +00001580
1581/* Receive Configuration Word */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001582#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1583#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1584#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1585#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1586#define E1000_RXCW_C 0x20000000 /* Receive config */
wdenk4e112c12003-06-03 23:54:09 +00001587#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001588#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
wdenk4e112c12003-06-03 23:54:09 +00001589
1590/* Transmit Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001591#define E1000_TCTL_RST 0x00000001 /* software reset */
1592#define E1000_TCTL_EN 0x00000002 /* enable tx */
1593#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1594#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1595#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
wdenk4e112c12003-06-03 23:54:09 +00001596#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1597#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001598#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
wdenk4e112c12003-06-03 23:54:09 +00001599#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1600#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
Roy Zang28f7a052009-07-31 13:34:02 +08001601#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
wdenk4e112c12003-06-03 23:54:09 +00001602
1603/* Receive Checksum Control */
1604#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1605#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1606#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1607#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1608
1609/* Definitions for power management and wakeup registers */
1610/* Wake Up Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001611#define E1000_WUC_APME 0x00000001 /* APM Enable */
wdenk4e112c12003-06-03 23:54:09 +00001612#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1613#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1614#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1615
1616/* Wake Up Filter Control */
1617#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001618#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1619#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1620#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1621#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1622#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
wdenk4e112c12003-06-03 23:54:09 +00001623#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1624#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1625#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1626#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1627#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1628#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1629#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1630#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1631#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1632
1633/* Wake Up Status */
1634#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1635#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1636#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1637#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1638#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1639#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1640#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1641#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1642#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1643#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1644#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1645#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1646#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1647
1648/* Management Control */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001649#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1650#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1651#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1652#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1653#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1654#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1655#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1656#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1657#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1658#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
wdenk4e112c12003-06-03 23:54:09 +00001659 * Filtering */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001660#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1661#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
wdenk4e112c12003-06-03 23:54:09 +00001662#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001663#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1664#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1665#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1666#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
wdenk4e112c12003-06-03 23:54:09 +00001667#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001668#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
wdenk4e112c12003-06-03 23:54:09 +00001669
1670#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1671#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1672
1673/* Wake Up Packet Length */
1674#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1675
Wolfgang Denka1be4762008-05-20 16:00:29 +02001676#define E1000_MDALIGN 4096
wdenk4e112c12003-06-03 23:54:09 +00001677
1678/* EEPROM Commands */
1679#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
1680#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
1681#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
1682#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
1683#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
1684
wdenk4e112c12003-06-03 23:54:09 +00001685/* Word definitions for ID LED Settings */
1686#define ID_LED_RESERVED_0000 0x0000
1687#define ID_LED_RESERVED_FFFF 0xFFFF
Wolfgang Denka1be4762008-05-20 16:00:29 +02001688#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
wdenk57b2d802003-06-27 21:31:46 +00001689 (ID_LED_OFF1_OFF2 << 8) | \
1690 (ID_LED_DEF1_DEF2 << 4) | \
1691 (ID_LED_DEF1_DEF2))
wdenk4e112c12003-06-03 23:54:09 +00001692#define ID_LED_DEF1_DEF2 0x1
1693#define ID_LED_DEF1_ON2 0x2
1694#define ID_LED_DEF1_OFF2 0x3
1695#define ID_LED_ON1_DEF2 0x4
Wolfgang Denka1be4762008-05-20 16:00:29 +02001696#define ID_LED_ON1_ON2 0x5
wdenk4e112c12003-06-03 23:54:09 +00001697#define ID_LED_ON1_OFF2 0x6
1698#define ID_LED_OFF1_DEF2 0x7
1699#define ID_LED_OFF1_ON2 0x8
1700#define ID_LED_OFF1_OFF2 0x9
1701
1702/* Mask bits for fields in Word 0x03 of the EEPROM */
1703#define EEPROM_COMPAT_SERVER 0x0400
1704#define EEPROM_COMPAT_CLIENT 0x0200
1705
1706/* Mask bits for fields in Word 0x0a of the EEPROM */
1707#define EEPROM_WORD0A_ILOS 0x0010
1708#define EEPROM_WORD0A_SWDPIO 0x01E0
1709#define EEPROM_WORD0A_LRST 0x0200
1710#define EEPROM_WORD0A_FD 0x0400
1711#define EEPROM_WORD0A_66MHZ 0x0800
1712
1713/* Mask bits for fields in Word 0x0f of the EEPROM */
1714#define EEPROM_WORD0F_PAUSE_MASK 0x3000
Wolfgang Denka1be4762008-05-20 16:00:29 +02001715#define EEPROM_WORD0F_PAUSE 0x1000
1716#define EEPROM_WORD0F_ASM_DIR 0x2000
1717#define EEPROM_WORD0F_ANE 0x0800
wdenk4e112c12003-06-03 23:54:09 +00001718#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1719
1720/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1721#define EEPROM_SUM 0xBABA
1722
1723/* EEPROM Map defines (WORD OFFSETS)*/
1724#define EEPROM_NODE_ADDRESS_BYTE_0 0
Wolfgang Denka1be4762008-05-20 16:00:29 +02001725#define EEPROM_PBA_BYTE_1 8
wdenk4e112c12003-06-03 23:54:09 +00001726
1727/* EEPROM Map Sizes (Byte Counts) */
1728#define PBA_SIZE 4
1729
1730/* Collision related configuration parameters */
Roy Zang28f7a052009-07-31 13:34:02 +08001731#define E1000_COLLISION_THRESHOLD 0xF
Wolfgang Denka1be4762008-05-20 16:00:29 +02001732#define E1000_CT_SHIFT 4
Roy Zang28f7a052009-07-31 13:34:02 +08001733#define E1000_COLLISION_DISTANCE 63
1734#define E1000_COLLISION_DISTANCE_82542 64
Wolfgang Denka1be4762008-05-20 16:00:29 +02001735#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1736#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
wdenk4e112c12003-06-03 23:54:09 +00001737#define E1000_GB_HDX_COLLISION_DISTANCE 512
Wolfgang Denka1be4762008-05-20 16:00:29 +02001738#define E1000_COLD_SHIFT 12
wdenk4e112c12003-06-03 23:54:09 +00001739
1740/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1741#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1742#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1743
1744/* Default values for the transmit IPG register */
1745#define DEFAULT_82542_TIPG_IPGT 10
1746#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1747#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1748
1749#define E1000_TIPG_IPGT_MASK 0x000003FF
1750#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1751#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1752
1753#define DEFAULT_82542_TIPG_IPGR1 2
1754#define DEFAULT_82543_TIPG_IPGR1 8
Wolfgang Denka1be4762008-05-20 16:00:29 +02001755#define E1000_TIPG_IPGR1_SHIFT 10
wdenk4e112c12003-06-03 23:54:09 +00001756
1757#define DEFAULT_82542_TIPG_IPGR2 10
1758#define DEFAULT_82543_TIPG_IPGR2 6
Roy Zang28f7a052009-07-31 13:34:02 +08001759#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
Wolfgang Denka1be4762008-05-20 16:00:29 +02001760#define E1000_TIPG_IPGR2_SHIFT 20
wdenk4e112c12003-06-03 23:54:09 +00001761
1762#define E1000_TXDMAC_DPP 0x00000001
1763
1764/* Adaptive IFS defines */
1765#define TX_THRESHOLD_START 8
1766#define TX_THRESHOLD_INCREMENT 10
1767#define TX_THRESHOLD_DECREMENT 1
1768#define TX_THRESHOLD_STOP 190
1769#define TX_THRESHOLD_DISABLE 0
1770#define TX_THRESHOLD_TIMER_MS 10000
Wolfgang Denka1be4762008-05-20 16:00:29 +02001771#define MIN_NUM_XMITS 1000
1772#define IFS_MAX 80
1773#define IFS_STEP 10
1774#define IFS_MIN 40
1775#define IFS_RATIO 4
wdenk4e112c12003-06-03 23:54:09 +00001776
1777/* PBA constants */
1778#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1779#define E1000_PBA_24K 0x0018
Roy Zang28f7a052009-07-31 13:34:02 +08001780#define E1000_PBA_38K 0x0026
wdenk4e112c12003-06-03 23:54:09 +00001781#define E1000_PBA_40K 0x0028
1782#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1783
1784/* Flow Control Constants */
1785#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1786#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
Wolfgang Denka1be4762008-05-20 16:00:29 +02001787#define FLOW_CONTROL_TYPE 0x8808
wdenk4e112c12003-06-03 23:54:09 +00001788
1789/* The historical defaults for the flow control values are given below. */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001790#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1791#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1792#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
wdenk4e112c12003-06-03 23:54:09 +00001793
1794/* Flow Control High-Watermark: 43464 bytes */
1795#define E1000_FC_HIGH_THRESH 0xA9C8
1796/* Flow Control Low-Watermark: 43456 bytes */
1797#define E1000_FC_LOW_THRESH 0xA9C0
1798/* Flow Control Pause Time: 858 usec */
1799#define E1000_FC_PAUSE_TIME 0x0680
1800
1801/* PCIX Config space */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001802#define PCIX_COMMAND_REGISTER 0xE6
wdenk4e112c12003-06-03 23:54:09 +00001803#define PCIX_STATUS_REGISTER_LO 0xE8
1804#define PCIX_STATUS_REGISTER_HI 0xEA
1805
1806#define PCIX_COMMAND_MMRBC_MASK 0x000C
1807#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1808#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1809#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1810#define PCIX_STATUS_HI_MMRBC_4K 0x3
1811#define PCIX_STATUS_HI_MMRBC_2K 0x2
1812
1813/* The number of bits that we need to shift right to move the "pause"
1814 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
wdenk57b2d802003-06-27 21:31:46 +00001815 * in the TXCW register
wdenk4e112c12003-06-03 23:54:09 +00001816 */
1817#define PAUSE_SHIFT 5
1818
1819/* The number of bits that we need to shift left to move the "SWDPIO"
1820 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
wdenk57b2d802003-06-27 21:31:46 +00001821 * in the CTRL register
wdenk4e112c12003-06-03 23:54:09 +00001822 */
1823#define SWDPIO_SHIFT 17
1824
1825/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1826 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1827 * Extended CTRL register.
wdenk57b2d802003-06-27 21:31:46 +00001828 * in the CTRL register
wdenk4e112c12003-06-03 23:54:09 +00001829 */
1830#define SWDPIO__EXT_SHIFT 4
1831
1832/* The number of bits that we need to shift left to move the "ILOS"
1833 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
wdenk57b2d802003-06-27 21:31:46 +00001834 * in the CTRL register
wdenk4e112c12003-06-03 23:54:09 +00001835 */
1836#define ILOS_SHIFT 3
1837
1838#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1839
1840/* The number of milliseconds we wait for auto-negotiation to complete */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001841#define LINK_UP_TIMEOUT 500
wdenk4e112c12003-06-03 23:54:09 +00001842
1843#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1844
1845/* The carrier extension symbol, as received by the NIC. */
1846#define CARRIER_EXTENSION 0x0F
1847
1848/* TBI_ACCEPT macro definition:
1849 *
1850 * This macro requires:
Wolfgang Denka1be4762008-05-20 16:00:29 +02001851 * adapter = a pointer to struct e1000_hw
1852 * status = the 8 bit status field of the RX descriptor with EOP set
1853 * error = the 8 bit error field of the RX descriptor with EOP set
1854 * length = the sum of all the length fields of the RX descriptors that
1855 * make up the current frame
1856 * last_byte = the last byte of the frame DMAed by the hardware
1857 * max_frame_length = the maximum frame length we want to accept.
1858 * min_frame_length = the minimum frame length we want to accept.
wdenk4e112c12003-06-03 23:54:09 +00001859 *
wdenk57b2d802003-06-27 21:31:46 +00001860 * This macro is a conditional that should be used in the interrupt
wdenk4e112c12003-06-03 23:54:09 +00001861 * handler's Rx processing routine when RxErrors have been detected.
1862 *
1863 * Typical use:
1864 * ...
1865 * if (TBI_ACCEPT) {
York Sun4a598092013-04-01 11:29:11 -07001866 * accept_frame = true;
Wolfgang Denka1be4762008-05-20 16:00:29 +02001867 * e1000_tbi_adjust_stats(adapter, MacAddress);
1868 * frame_length--;
wdenk4e112c12003-06-03 23:54:09 +00001869 * } else {
York Sun4a598092013-04-01 11:29:11 -07001870 * accept_frame = false;
wdenk4e112c12003-06-03 23:54:09 +00001871 * }
1872 * ...
1873 */
1874
1875#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1876 ((adapter)->tbi_compatibility_on && \
1877 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1878 ((last_byte) == CARRIER_EXTENSION) && \
1879 (((status) & E1000_RXD_STAT_VP) ? \
wdenk57b2d802003-06-27 21:31:46 +00001880 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1881 ((length) <= ((adapter)->max_frame_size + 1))) : \
1882 (((length) > (adapter)->min_frame_size) && \
1883 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
wdenk4e112c12003-06-03 23:54:09 +00001884
1885/* Structures, enums, and macros for the PHY */
1886
1887/* Bit definitions for the Management Data IO (MDIO) and Management Data
1888 * Clock (MDC) pins in the Device Control Register.
1889 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001890#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1891#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1892#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1893#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1894#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1895#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1896#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1897#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
wdenk4e112c12003-06-03 23:54:09 +00001898
1899/* PHY 1000 MII Register/Bit Definitions */
1900/* PHY Registers defined by IEEE */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001901#define PHY_CTRL 0x00 /* Control Register */
1902#define PHY_STATUS 0x01 /* Status Regiser */
1903#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1904#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1905#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1906#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1907#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1908#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1909#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1910#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1911#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1912#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
wdenk4e112c12003-06-03 23:54:09 +00001913
1914/* M88E1000 Specific Registers */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001915#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1916#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1917#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1918#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1919#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1920#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
wdenk4e112c12003-06-03 23:54:09 +00001921
Roy Zang28f7a052009-07-31 13:34:02 +08001922#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1923#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1924
Wolfgang Denka1be4762008-05-20 16:00:29 +02001925#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
Andre Schwarz68c2a302008-03-06 16:45:44 +01001926
Roy Zang28f7a052009-07-31 13:34:02 +08001927/* M88EC018 Rev 2 specific DownShift settings */
1928#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1929#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1930#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1931#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1932#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1933#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1934#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1935#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1936#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1937
Andre Schwarz68c2a302008-03-06 16:45:44 +01001938/* IGP01E1000 specifics */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001939#define IGP01E1000_IEEE_REGS_PAGE 0x0000
Andre Schwarz68c2a302008-03-06 16:45:44 +01001940#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
Wolfgang Denka1be4762008-05-20 16:00:29 +02001941#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
Andre Schwarz68c2a302008-03-06 16:45:44 +01001942
1943/* IGP01E1000 Specific Registers */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001944#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1945#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1946#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1947#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1948#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1949#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1950#define IGP02E1000_PHY_POWER_MGMT 0x19
1951#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
wdenk4e112c12003-06-03 23:54:09 +00001952
Roy Zang28f7a052009-07-31 13:34:02 +08001953/* IGP01E1000 AGC Registers - stores the cable length values*/
1954#define IGP01E1000_PHY_AGC_A 0x1172
1955#define IGP01E1000_PHY_AGC_B 0x1272
1956#define IGP01E1000_PHY_AGC_C 0x1472
1957#define IGP01E1000_PHY_AGC_D 0x1872
1958
1959/* IGP01E1000 Specific Port Config Register - R/W */
1960#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
1961#define IGP01E1000_PSCFR_PRE_EN 0x0020
1962#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
1963#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
1964#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
1965#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
1966/* IGP02E1000 AGC Registers for cable length values */
1967#define IGP02E1000_PHY_AGC_A 0x11B1
1968#define IGP02E1000_PHY_AGC_B 0x12B1
1969#define IGP02E1000_PHY_AGC_C 0x14B1
1970#define IGP02E1000_PHY_AGC_D 0x18B1
1971
1972#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
1973#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
1974 non-D0a modes */
1975#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
1976 D0a mode */
1977
1978/* IGP01E1000 DSP Reset Register */
1979#define IGP01E1000_PHY_DSP_RESET 0x1F33
1980#define IGP01E1000_PHY_DSP_SET 0x1F71
1981#define IGP01E1000_PHY_DSP_FFE 0x1F35
1982
1983#define IGP01E1000_PHY_CHANNEL_NUM 4
1984#define IGP02E1000_PHY_CHANNEL_NUM 4
1985
1986#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1987#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1988#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1989#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1990
1991#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1992#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1993
1994#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1995#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1996#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1997#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1998
1999#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2000/* IGP01E1000 PCS Initialization register - stores the polarity status when
2001 * speed = 1000 Mbps. */
2002#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2003#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2004
2005#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2006
2007/* IGP01E1000 GMII FIFO Register */
2008#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2009 * on Link-Up */
2010#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2011
2012/* IGP01E1000 Analog Register */
2013#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2014#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2015#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2016#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2017
2018#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2019#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2020#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2021#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2022#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2023
2024#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2025#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2026#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2027#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2028
2029/* IGP01E1000 Specific Port Control Register - R/W */
2030#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2031#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2032#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2033#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2034#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2035#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2036/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2037#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
2038#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
2039 Disabled */
2040#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
2041#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
2042 Disabled */
2043#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2044#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
2045 configuration */
2046#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
2047 configuration */
2048#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
2049 crossover */
2050#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
2051 Distance */
2052#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
2053#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
2054#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
2055 (Energy Detect) */
2056#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
2057#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
2058#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
2059#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
2060#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
2061
2062/* PHY Specific Status Register (Page 0, Register 17) */
2063#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
2064#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
2065#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
2066#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
2067#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
2068#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
2069#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
2070#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
2071#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
2072#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
2073#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2074#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2075#define GG82563_PSSR_SPEED_MASK 0xC000
2076#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
2077#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
2078#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
2079
2080/* PHY Specific Status Register 2 (Page 0, Register 19) */
2081#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
2082#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
2083#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
2084#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
2085#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
York Sun4a598092013-04-01 11:29:11 -07002086#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */
Roy Zang28f7a052009-07-31 13:34:02 +08002087#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
2088#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
2089#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2090#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2091#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
2092#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
2093#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2094
2095/* PHY Specific Control Register 2 (Page 0, Register 26) */
2096#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
2097 Polarity */
2098#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
2099#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
2100 Operation */
2101#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
2102 Sequence */
2103#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
2104 Sequence */
2105#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
2106 Auto-Negotiation */
2107#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
2108 1000BASE-T */
2109#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2110#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
2111#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
2112
2113/* MAC Specific Control Register (Page 2, Register 21) */
2114/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2115#define GG82563_MSCR_TX_CLK_MASK 0x0007
2116#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2117#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2118#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2119#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2120
2121#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2122
2123/* DSP Distance Register (Page 5, Register 26) */
2124#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
2125 1 = 50-80M;
2126 2 = 80-110M;
2127 3 = 110-140M;
2128 4 = >140M */
2129
2130/* Kumeran Mode Control Register (Page 193, Register 16) */
2131#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
2132 0=Kumeran Inband LEDs */
2133#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
2134#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
2135#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
2136#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
2137 0=0.8MHz */
2138#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2139
2140/* Power Management Control Register (Page 193, Register 20) */
2141#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
2142 Electrical Idle */
2143#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
2144#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
2145#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
2146 Auto-Negotiation */
2147#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
2148 Auto-Neg in non D0 */
2149#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
2150 Auto-Neg Always */
2151#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
2152 Reverse Auto-Negotiation */
2153#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
2154#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
2155#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
2156#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
2157#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
2158#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
2159
2160/* In-Band Control Register (Page 194, Register 18) */
2161#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
2162
2163
2164/* Bits...
2165 * 15-5: page
2166 * 4-0: register offset
2167 */
2168#define GG82563_PAGE_SHIFT 5
2169#define GG82563_REG(page, reg) \
2170 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2171#define GG82563_MIN_ALT_REG 30
2172
2173/* GG82563 Specific Registers */
2174#define GG82563_PHY_SPEC_CTRL \
2175 GG82563_REG(0, 16) /* PHY Specific Control */
2176#define GG82563_PHY_SPEC_STATUS \
2177 GG82563_REG(0, 17) /* PHY Specific Status */
2178#define GG82563_PHY_INT_ENABLE \
2179 GG82563_REG(0, 18) /* Interrupt Enable */
2180#define GG82563_PHY_SPEC_STATUS_2 \
2181 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2182#define GG82563_PHY_RX_ERR_CNTR \
2183 GG82563_REG(0, 21) /* Receive Error Counter */
2184#define GG82563_PHY_PAGE_SELECT \
2185 GG82563_REG(0, 22) /* Page Select */
2186#define GG82563_PHY_SPEC_CTRL_2 \
2187 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2188#define GG82563_PHY_PAGE_SELECT_ALT \
2189 GG82563_REG(0, 29) /* Alternate Page Select */
2190#define GG82563_PHY_TEST_CLK_CTRL \
2191 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2192
2193#define GG82563_PHY_MAC_SPEC_CTRL \
2194 GG82563_REG(2, 21) /* MAC Specific Control Register */
2195#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2196 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2197
2198#define GG82563_PHY_DSP_DISTANCE \
2199 GG82563_REG(5, 26) /* DSP Distance */
2200
2201/* Page 193 - Port Control Registers */
2202#define GG82563_PHY_KMRN_MODE_CTRL \
2203 GG82563_REG(193, 16) /* Kumeran Mode Control */
2204#define GG82563_PHY_PORT_RESET \
2205 GG82563_REG(193, 17) /* Port Reset */
2206#define GG82563_PHY_REVISION_ID \
2207 GG82563_REG(193, 18) /* Revision ID */
2208#define GG82563_PHY_DEVICE_ID \
2209 GG82563_REG(193, 19) /* Device ID */
2210#define GG82563_PHY_PWR_MGMT_CTRL \
2211 GG82563_REG(193, 20) /* Power Management Control */
2212#define GG82563_PHY_RATE_ADAPT_CTRL \
2213 GG82563_REG(193, 25) /* Rate Adaptation Control */
2214
2215/* Page 194 - KMRN Registers */
2216#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2217 GG82563_REG(194, 16) /* FIFO's Control/Status */
2218#define GG82563_PHY_KMRN_CTRL \
2219 GG82563_REG(194, 17) /* Control */
2220#define GG82563_PHY_INBAND_CTRL \
2221 GG82563_REG(194, 18) /* Inband Control */
2222#define GG82563_PHY_KMRN_DIAGNOSTIC \
2223 GG82563_REG(194, 19) /* Diagnostic */
2224#define GG82563_PHY_ACK_TIMEOUTS \
2225 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2226#define GG82563_PHY_ADV_ABILITY \
2227 GG82563_REG(194, 21) /* Advertised Ability */
2228#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2229 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2230#define GG82563_PHY_ADV_NEXT_PAGE \
2231 GG82563_REG(194, 24) /* Advertised Next Page */
2232#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2233 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2234#define GG82563_PHY_KMRN_MISC \
2235 GG82563_REG(194, 26) /* Misc. */
2236
wdenk4e112c12003-06-03 23:54:09 +00002237/* PHY Control Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002238#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2239#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2240#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2241#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2242#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2243#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2244#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2245#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2246#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2247#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
wdenk4e112c12003-06-03 23:54:09 +00002248
2249/* PHY Status Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002250#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2251#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2252#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2253#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2254#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2255#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2256#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2257#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2258#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2259#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2260#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2261#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2262#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2263#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2264#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
wdenk4e112c12003-06-03 23:54:09 +00002265
2266/* Autoneg Advertisement Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002267#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2268#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2269#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2270#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2271#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2272#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2273#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2274#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2275#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2276#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
wdenk4e112c12003-06-03 23:54:09 +00002277
2278/* Link Partner Ability Register (Base Page) */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002279#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2280#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2281#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2282#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2283#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2284#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2285#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2286#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2287#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2288#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2289#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
wdenk4e112c12003-06-03 23:54:09 +00002290
2291/* Autoneg Expansion Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002292#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2293#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2294#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2295#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2296#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
wdenk4e112c12003-06-03 23:54:09 +00002297
2298/* Next Page TX Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002299#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2300#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2301 * of different NP
2302 */
2303#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2304 * 0 = cannot comply with msg
2305 */
2306#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2307#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2308 * 0 = sending last NP
2309 */
wdenk4e112c12003-06-03 23:54:09 +00002310
2311/* Link Partner Next Page Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002312#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2313#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2314 * of different NP
2315 */
2316#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2317 * 0 = cannot comply with msg
2318 */
2319#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2320#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2321#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2322 * 0 = sending last NP
2323 */
wdenk4e112c12003-06-03 23:54:09 +00002324
2325/* 1000BASE-T Control Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002326#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2327#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2328#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2329#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2330 /* 0=DTE device */
2331#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2332 /* 0=Configure PHY as Slave */
2333#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2334 /* 0=Automatic Master/Slave config */
2335#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2336#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2337#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2338#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2339#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
wdenk4e112c12003-06-03 23:54:09 +00002340
2341/* 1000BASE-T Status Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002342#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2343#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2344#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2345#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2346#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2347#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2348#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2349#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
wdenk4e112c12003-06-03 23:54:09 +00002350#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
Wolfgang Denka1be4762008-05-20 16:00:29 +02002351#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
wdenk4e112c12003-06-03 23:54:09 +00002352
2353/* Extended Status Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002354#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2355#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2356#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2357#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
wdenk4e112c12003-06-03 23:54:09 +00002358
Wolfgang Denka1be4762008-05-20 16:00:29 +02002359#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2360#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
wdenk4e112c12003-06-03 23:54:09 +00002361
Wolfgang Denka1be4762008-05-20 16:00:29 +02002362#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2363 /* (0=enable, 1=disable) */
wdenk4e112c12003-06-03 23:54:09 +00002364
2365/* M88E1000 PHY Specific Control Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002366#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
wdenk4e112c12003-06-03 23:54:09 +00002367#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002368#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2369#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
wdenk4e112c12003-06-03 23:54:09 +00002370 * 0=CLK125 toggling
2371 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002372#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2373 /* Manual MDI configuration */
2374#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2375#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
wdenk57b2d802003-06-27 21:31:46 +00002376 * 100BASE-TX/10BASE-T:
wdenk4e112c12003-06-03 23:54:09 +00002377 * MDI Mode
2378 */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002379#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
wdenk57b2d802003-06-27 21:31:46 +00002380 * all speeds.
wdenk4e112c12003-06-03 23:54:09 +00002381 */
2382#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
Wolfgang Denka1be4762008-05-20 16:00:29 +02002383 /* 1=Enable Extended 10BASE-T distance
2384 * (Lower 10BASE-T RX Threshold)
2385 * 0=Normal 10BASE-T RX Threshold */
2386#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2387 /* 1=5-Bit interface in 100BASE-TX
2388 * 0=MII interface in 100BASE-TX */
2389#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2390#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2391#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
wdenk4e112c12003-06-03 23:54:09 +00002392
Wolfgang Denka1be4762008-05-20 16:00:29 +02002393#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2394#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
wdenk4e112c12003-06-03 23:54:09 +00002395#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2396
2397/* M88E1000 PHY Specific Status Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002398#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2399#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2400#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2401#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2402 * 3=110-140M;4=>140M */
2403#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2404#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2405#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2406#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2407#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2408#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2409#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2410#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
wdenk4e112c12003-06-03 23:54:09 +00002411
2412#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
Wolfgang Denka1be4762008-05-20 16:00:29 +02002413#define M88E1000_PSSR_MDIX_SHIFT 6
wdenk4e112c12003-06-03 23:54:09 +00002414#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2415
2416/* M88E1000 Extended PHY Specific Control Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002417#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2418#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
wdenk4e112c12003-06-03 23:54:09 +00002419 * Will assert lost lock and bring
2420 * link down if idle not seen
wdenk57b2d802003-06-27 21:31:46 +00002421 * within 1ms in 1000BASE-T
wdenk4e112c12003-06-03 23:54:09 +00002422 */
2423/* Number of times we will attempt to autonegotiate before downshifting if we
2424 * are the master */
2425#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2426#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2427#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2428#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2429#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2430/* Number of times we will attempt to autonegotiate before downshifting if we
2431 * are the slave */
2432#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2433#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2434#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2435#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2436#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
Wolfgang Denka1be4762008-05-20 16:00:29 +02002437#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2438#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2439#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
wdenk4e112c12003-06-03 23:54:09 +00002440
2441/* Bit definitions for valid PHY IDs. */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002442#define M88E1000_E_PHY_ID 0x01410C50
2443#define M88E1000_I_PHY_ID 0x01410C30
2444#define M88E1011_I_PHY_ID 0x01410C20
2445#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2446#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2447#define IGP01E1000_I_PHY_ID 0x02A80380
Roy Zang28f7a052009-07-31 13:34:02 +08002448#define M88E1011_I_REV_4 0x04
2449#define M88E1111_I_PHY_ID 0x01410CC0
2450#define L1LXT971A_PHY_ID 0x001378E0
2451#define GG82563_E_PHY_ID 0x01410CA0
wdenk4e112c12003-06-03 23:54:09 +00002452
Roy Zang181119b2011-01-21 11:29:38 +08002453#define BME1000_E_PHY_ID 0x01410CB0
2454
Marek Vasut74a13c22014-08-08 07:41:39 -07002455#define I210_I_PHY_ID 0x01410C00
2456
wdenk4e112c12003-06-03 23:54:09 +00002457/* Miscellaneous PHY bit definitions. */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002458#define PHY_PREAMBLE 0xFFFFFFFF
2459#define PHY_SOF 0x01
2460#define PHY_OP_READ 0x02
2461#define PHY_OP_WRITE 0x01
2462#define PHY_TURNAROUND 0x02
2463#define PHY_PREAMBLE_SIZE 32
2464#define MII_CR_SPEED_1000 0x0040
2465#define MII_CR_SPEED_100 0x2000
2466#define MII_CR_SPEED_10 0x0000
2467#define E1000_PHY_ADDRESS 0x01
Stefan Roese497c7312015-08-11 17:12:44 +02002468#define PHY_AUTO_NEG_TIME 80 /* 8.0 Seconds */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002469#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2470#define PHY_REVISION_MASK 0xFFFFFFF0
2471#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2472#define REG4_SPEED_MASK 0x01E0
2473#define REG9_SPEED_MASK 0x0300
2474#define ADVERTISE_10_HALF 0x0001
2475#define ADVERTISE_10_FULL 0x0002
2476#define ADVERTISE_100_HALF 0x0004
2477#define ADVERTISE_100_FULL 0x0008
2478#define ADVERTISE_1000_HALF 0x0010
2479#define ADVERTISE_1000_FULL 0x0020
wdenk4e112c12003-06-03 23:54:09 +00002480
Roy Zang28f7a052009-07-31 13:34:02 +08002481#define ICH_FLASH_GFPREG 0x0000
2482#define ICH_FLASH_HSFSTS 0x0004
2483#define ICH_FLASH_HSFCTL 0x0006
2484#define ICH_FLASH_FADDR 0x0008
2485#define ICH_FLASH_FDATA0 0x0010
2486#define ICH_FLASH_FRACC 0x0050
2487#define ICH_FLASH_FREG0 0x0054
2488#define ICH_FLASH_FREG1 0x0058
2489#define ICH_FLASH_FREG2 0x005C
2490#define ICH_FLASH_FREG3 0x0060
2491#define ICH_FLASH_FPR0 0x0074
2492#define ICH_FLASH_FPR1 0x0078
2493#define ICH_FLASH_SSFSTS 0x0090
2494#define ICH_FLASH_SSFCTL 0x0092
2495#define ICH_FLASH_PREOP 0x0094
2496#define ICH_FLASH_OPTYPE 0x0096
2497#define ICH_FLASH_OPMENU 0x0098
2498
2499#define ICH_FLASH_REG_MAPSIZE 0x00A0
2500#define ICH_FLASH_SECTOR_SIZE 4096
2501#define ICH_GFPREG_BASE_MASK 0x1FFF
2502#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
2503
Roy Zang28f7a052009-07-31 13:34:02 +08002504#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
2505
2506/* SPI EEPROM Status Register */
2507#define EEPROM_STATUS_RDY_SPI 0x01
2508#define EEPROM_STATUS_WEN_SPI 0x02
2509#define EEPROM_STATUS_BP0_SPI 0x04
2510#define EEPROM_STATUS_BP1_SPI 0x08
2511#define EEPROM_STATUS_WPEN_SPI 0x80
2512
2513/* SW Semaphore Register */
2514#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2515#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2516#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2517#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2518
2519/* FW Semaphore Register */
2520#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2521#define E1000_FWSM_MODE_SHIFT 1
2522#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2523
2524#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2525#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2526#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2527#define E1000_FWSM_SKUEL_SHIFT 29
2528#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2529#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2530#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2531#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2532
2533#define E1000_GCR 0x05B00 /* PCI-Ex Control */
2534#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
2535#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
2536#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
2537#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
2538#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
2539#define E1000_SWSM 0x05B50 /* SW Semaphore */
2540#define E1000_FWSM 0x05B54 /* FW Semaphore */
2541#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
2542#define E1000_HICR 0x08F00 /* Host Inteface Control */
2543
2544#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2545#define IGP_ACTIVITY_LED_ENABLE 0x0300
2546#define IGP_LED3_MODE 0x07000000
2547
2548/* Mask bit for PHY class in Word 7 of the EEPROM */
2549#define EEPROM_PHY_CLASS_A 0x8000
2550#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2551#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2552#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2553
2554#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
2555#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
2556#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
2557#define E1000_KUMCTRLSTA_REN 0x00200000
2558
2559#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
2560#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
2561#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
2562#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
2563#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
2564#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
2565#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
2566#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
2567#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
2568
2569/* FIFO Control */
2570#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
2571#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
2572
2573/* In-Band Control */
2574#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
2575#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
2576
2577/* Half-Duplex Control */
2578#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
2579#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
2580
2581#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
2582
2583#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
2584#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
2585
2586#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
2587#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
2588#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
2589
2590#define E1000_MNG_ICH_IAMT_MODE 0x2
2591#define E1000_MNG_IAMT_MODE 0x3
2592#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2593#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
2594/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2595#define PHY_CFG_TIMEOUT 100
2596#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2597#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
Roy Zang28f7a052009-07-31 13:34:02 +08002598#define AUTO_ALL_MODES 0
2599
2600#ifndef E1000_MASTER_SLAVE
2601/* Switch to override PHY master/slave setting */
2602#define E1000_MASTER_SLAVE e1000_ms_hw_default
2603#endif
2604/* Extended Transmit Control */
2605#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2606#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2607
2608#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2609
2610#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2611
2612#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2613#define E1000_MC_TBL_SIZE_ICH8LAN 32
2614
2615#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
2616 after IMS clear */
Wolfgang Denka1be4762008-05-20 16:00:29 +02002617#endif /* _E1000_HW_H_ */