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git01.mediatek.com / filogic / uboot / 8251e0337c7b16446c96a13cab57ba1af82676ce / . / arch / arm / dts / imx8mq-phanbell.dts
blob: 4892ad5ee1c06a8b9bbfb8063507f9206a9c87a6 [file] [log] [blame]
Alifer Moraesa0a29482020-03-06 07:46:33 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mq.dtsi"
9
10/ {
11 model = "Google i.MX8MQ Phanbell";
12 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x00000000 0x40000000 0 0x40000000>;
21 };
22
23 pmic_osc: clock-pmic {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <32768>;
27 clock-output-names = "pmic_osc";
28 };
29
30 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
31 compatible = "regulator-fixed";
32 regulator-name = "VSD_3V3";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
36 enable-active-high;
37 };
38};
39
40&A53_0 {
41 cpu-supply = <&buck2>;
42};
43
44&A53_1 {
45 cpu-supply = <&buck2>;
46};
47
48&A53_2 {
49 cpu-supply = <&buck2>;
50};
51
52&A53_3 {
53 cpu-supply = <&buck2>;
54};
55
56&i2c1 {
57 clock-frequency = <400000>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_i2c1>;
60 status = "okay";
61
62 pmic: pmic@4b {
63 compatible = "rohm,bd71837";
64 reg = <0x4b>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_pmic>;
67 #clock-cells = <0>;
68 clocks = <&pmic_osc>;
69 clock-output-names = "pmic_clk";
70 interrupt-parent = <&gpio1>;
71 interrupts = <3 GPIO_ACTIVE_LOW>;
72
73 regulators {
74 buck1: BUCK1 {
75 regulator-name = "buck1";
76 regulator-min-microvolt = <700000>;
77 regulator-max-microvolt = <1300000>;
78 regulator-boot-on;
79 regulator-always-on;
80 regulator-ramp-delay = <1250>;
81 rohm,dvs-run-voltage = <900000>;
82 rohm,dvs-idle-voltage = <900000>;
83 rohm,dvs-suspend-voltage = <800000>;
84 };
85
86 buck2: BUCK2 {
87 regulator-name = "buck2";
88 regulator-min-microvolt = <850000>;
89 regulator-max-microvolt = <1000000>;
90 regulator-boot-on;
91 regulator-always-on;
92 rohm,dvs-run-voltage = <1000000>;
93 rohm,dvs-idle-voltage = <900000>;
94 };
95
96 buck3: BUCK3 {
97 regulator-name = "buck3";
98 regulator-min-microvolt = <700000>;
99 regulator-max-microvolt = <1300000>;
100 regulator-boot-on;
101 rohm,dvs-run-voltage = <900000>;
102 };
103
104 buck4: BUCK4 {
105 regulator-name = "buck4";
106 regulator-min-microvolt = <700000>;
107 regulator-max-microvolt = <1300000>;
108 regulator-boot-on;
109 regulator-always-on;
110 rohm,dvs-run-voltage = <900000>;
111 };
112
113 buck5: BUCK5 {
114 regulator-name = "buck5";
115 regulator-min-microvolt = <700000>;
116 regulator-max-microvolt = <1350000>;
117 regulator-boot-on;
118 regulator-always-on;
119 };
120
121 buck6: BUCK6 {
122 regulator-name = "buck6";
123 regulator-min-microvolt = <3000000>;
124 regulator-max-microvolt = <3300000>;
125 regulator-boot-on;
126 regulator-always-on;
127 };
128
129 buck7: BUCK7 {
130 regulator-name = "buck7";
131 regulator-min-microvolt = <1605000>;
132 regulator-max-microvolt = <1995000>;
133 regulator-boot-on;
134 regulator-always-on;
135 };
136
137 buck8: BUCK8 {
138 regulator-name = "buck8";
139 regulator-min-microvolt = <800000>;
140 regulator-max-microvolt = <1400000>;
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 ldo1: LDO1 {
146 regulator-name = "ldo1";
147 regulator-min-microvolt = <3000000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-boot-on;
150 regulator-always-on;
151 };
152
153 ldo2: LDO2 {
154 regulator-name = "ldo2";
155 regulator-min-microvolt = <900000>;
156 regulator-max-microvolt = <900000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 ldo3: LDO3 {
162 regulator-name = "ldo3";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-boot-on;
166 regulator-always-on;
167 };
168
169 ldo4: LDO4 {
170 regulator-name = "ldo4";
171 regulator-min-microvolt = <900000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 ldo5: LDO5 {
178 regulator-name = "ldo5";
179 regulator-min-microvolt = <1800000>;
180 regulator-max-microvolt = <3300000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 ldo6: LDO6 {
186 regulator-name = "ldo6";
187 regulator-min-microvolt = <900000>;
188 regulator-max-microvolt = <1800000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo7: LDO7 {
194 regulator-name = "ldo7";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3300000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200 };
201 };
202};
203
204&fec1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_fec1>;
207 phy-mode = "rgmii-id";
208 phy-handle = <&ethphy0>;
209 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
210 phy-reset-duration = <10>;
211 phy-reset-post-delay = <50>;
212 fsl,magic-packet;
213 status = "okay";
214
215 mdio {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet-phy-ieee802.3-c22";
220 reg = <0>;
221 };
222 };
223};
224
225&uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay";
229};
230
231&usdhc1 {
232 pinctrl-names = "default", "state_100mhz", "state_200mhz";
233 pinctrl-0 = <&pinctrl_usdhc1>;
234 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
235 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
236 bus-width = <8>;
237 non-removable;
238 status = "okay";
239};
240
241&usdhc2 {
242 pinctrl-names = "default", "state_100mhz", "state_200mhz";
243 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
244 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
245 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
246 bus-width = <4>;
247 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
248 vmmc-supply = <&reg_usdhc2_vmmc>;
249 status = "okay";
250};
251
252&usb3_phy0 {
253 status = "okay";
254};
255
256&usb_dwc3_0 {
257 dr_mode = "otg";
258 status = "okay";
259};
260
261&usb3_phy1 {
262 status = "okay";
263};
264
265&usb_dwc3_1 {
266 dr_mode = "host";
267 status = "okay";
268};
269
270&wdog1 {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_wdog>;
273 fsl,ext-reset-output;
274 status = "okay";
275};
276
277&iomuxc {
278 pinctrl_fec1: fec1grp {
279 fsl,pins = <
280 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
281 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
282 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
283 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
284 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
285 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
286 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
287 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
288 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
289 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
290 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
291 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
292 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
293 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
294 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
295 >;
296 };
297
298 pinctrl_i2c1: i2c1grp {
299 fsl,pins = <
300 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
301 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
302 >;
303 };
304
305 pinctrl_pmic: pmicirq {
306 fsl,pins = <
307 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
308 >;
309 };
310
311 pinctrl_uart1: uart1grp {
312 fsl,pins = <
313 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
314 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
315 >;
316 };
317
318 pinctrl_usdhc1: usdhc1grp {
319 fsl,pins = <
320 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
321 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
322 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
323 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
324 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
325 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
326 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
327 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
328 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
329 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
330 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
331 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
332 >;
333 };
334
335 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
336 fsl,pins = <
337 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
338 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
339 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
340 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
341 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
342 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
343 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
344 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
345 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
346 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
347 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
348 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
349 >;
350 };
351
352 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
353 fsl,pins = <
354 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
355 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
356 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
357 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
358 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
359 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
360 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
361 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
362 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
363 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
364 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
365 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
366 >;
367 };
368
369 pinctrl_usdhc2_gpio: usdhc2grpgpio {
370 fsl,pins = <
371 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
372 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
373 >;
374 };
375
376 pinctrl_usdhc2: usdhc2grp {
377 fsl,pins = <
378 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
379 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
380 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
381 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
382 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
383 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
384 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
385 >;
386 };
387
388 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
389 fsl,pins = <
390 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
391 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
392 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
393 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
394 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
395 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
396 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
397 >;
398 };
399
400 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
401 fsl,pins = <
402 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
403 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
404 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
405 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
406 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
407 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
408 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
409 >;
410 };
411
412 pinctrl_wdog: wdoggrp {
413 fsl,pins = <
414 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
415 >;
416 };
417};