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git01.mediatek.com / filogic / uboot / 8251e0337c7b16446c96a13cab57ba1af82676ce / . / arch / arm / dts / imx6-apalis.dts
blob: 72f7439aed2e9840fcf83f1a282ec09d3e92f9ca [file] [log] [blame]
Marcel Ziswiler4a31e8d2019-02-08 18:12:09 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include "imx6q.dtsi"
9
10/ {
11 model = "Toradex Apalis iMX6Q/D";
12 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
13
14 /* Will be filled by the bootloader */
15 memory@10000000 {
16 device_type = "memory";
17 reg = <0x10000000 0>;
18 };
19
20 aliases {
21 mmc0 = &usdhc3;
22 mmc1 = &usdhc1;
23 mmc2 = &usdhc2;
24 usb0 = &usbotg; /* required for ums */
Igor Opaniuk131ebd72019-11-04 11:12:01 +0100[diff] [blame]25 ethernet0 = &fec;
Marcel Ziswiler4a31e8d2019-02-08 18:12:09 +0100[diff] [blame]26 };
27
28 chosen {
29 stdout-path = &uart1;
30 };
31
32 reg_module_3v3: regulator-module-3v3 {
33 compatible = "regulator-fixed";
34 regulator-name = "+V3.3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 regulator-always-on;
38 };
39
40 reg_usb_otg_vbus: regulator-usb-otg-vbus {
41 compatible = "regulator-fixed";
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
44 regulator-name = "usb_otg_vbus";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */
48 enable-active-high;
49 };
50
51 /* on-module USB hub */
52 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
53 compatible = "regulator-fixed";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
56 regulator-name = "usb_host_vbus_hub";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
60 startup-delay-us = <2000>;
61 enable-active-high;
62 };
63
64 reg_usb_host_vbus: regulator-usb-host-vbus {
65 compatible = "regulator-fixed";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
68 regulator-name = "usb_host_vbus";
69 regulator-min-microvolt = <5000000>;
70 regulator-max-microvolt = <5000000>;
71 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */
72 enable-active-high;
73 vin-supply = <&reg_usb_host_vbus_hub>;
74 };
75};
76
77/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
78&i2c1 {
79 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c1>;
82 status = "okay";
83};
84
85/*
86 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
87 * touch screen controller
88 */
89&i2c2 {
90 clock-frequency = <100000>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_i2c2>;
93 status = "okay";
94
95 pmic: pfuze100@8 {
96 compatible = "fsl,pfuze100";
97 reg = <0x08>;
98
99 regulators {
100 sw1a_reg: sw1ab {
101 regulator-min-microvolt = <300000>;
102 regulator-max-microvolt = <1875000>;
103 regulator-boot-on;
104 regulator-always-on;
105 regulator-ramp-delay = <6250>;
106 };
107
108 sw1c_reg: sw1c {
109 regulator-min-microvolt = <300000>;
110 regulator-max-microvolt = <1875000>;
111 regulator-boot-on;
112 regulator-always-on;
113 regulator-ramp-delay = <6250>;
114 };
115
116 sw3a_reg: sw3a {
117 regulator-min-microvolt = <400000>;
118 regulator-max-microvolt = <1975000>;
119 regulator-boot-on;
120 regulator-always-on;
121 };
122
123 swbst_reg: swbst {
124 regulator-min-microvolt = <5000000>;
125 regulator-max-microvolt = <5150000>;
126 regulator-boot-on;
127 regulator-always-on;
128 };
129
130 snvs_reg: vsnvs {
131 regulator-min-microvolt = <1000000>;
132 regulator-max-microvolt = <3000000>;
133 regulator-boot-on;
134 regulator-always-on;
135 };
136
137 vref_reg: vrefddr {
138 regulator-boot-on;
139 regulator-always-on;
140 };
141
142 vgen1_reg: vgen1 {
143 regulator-min-microvolt = <800000>;
144 regulator-max-microvolt = <1550000>;
145 regulator-boot-on;
146 regulator-always-on;
147 };
148
149 vgen2_reg: vgen2 {
150 regulator-min-microvolt = <800000>;
151 regulator-max-microvolt = <1550000>;
152 regulator-boot-on;
153 regulator-always-on;
154 };
155
156 vgen3_reg: vgen3 {
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <3300000>;
159 regulator-boot-on;
160 regulator-always-on;
161 };
162
163 vgen4_reg: vgen4 {
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 vgen5_reg: vgen5 {
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 vgen6_reg: vgen6 {
178 regulator-min-microvolt = <1800000>;
179 regulator-max-microvolt = <3300000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183 };
184 };
185};
186
187/*
188 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
189 * board)
190 */
191&i2c3 {
192 clock-frequency = <100000>;
193 pinctrl-names = "default", "gpio";
194 pinctrl-0 = <&pinctrl_i2c3>;
195 pinctrl-1 = <&pinctrl_i2c3_recovery>;
196 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
197 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
198 status = "okay";
199};
200
Igor Opaniuk131ebd72019-11-04 11:12:01 +0100[diff] [blame]201&fec {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_enet>;
204 phy-mode = "rgmii";
205 phy-handle = <&ethphy>;
206 phy-reset-duration = <10>;
207 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
208 status = "okay";
209
210 mdio {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 ethphy: ethernet-phy@7 {
215 interrupt-parent = <&gpio1>;
216 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
217 reg = <7>;
218 };
219 };
220};
221
Marcel Ziswiler4a31e8d2019-02-08 18:12:09 +0100[diff] [blame]222/* Apalis Serial ATA */
223&sata {
224 status = "okay";
225};
226
227/* Apalis UART1 */
228&uart1 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
231 fsl,dte-mode;
232 uart-has-rtscts;
233 status = "okay";
234};
235
236/* Apalis UART2 */
237&uart2 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_uart2_dte>;
240 fsl,dte-mode;
241 uart-has-rtscts;
242 status = "okay";
243};
244
245/* Apalis UART3 */
246&uart4 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart4_dte>;
249 fsl,dte-mode;
250 status = "okay";
251};
252
253/* Apalis UART4 */
254&uart5 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart5_dte>;
257 fsl,dte-mode;
258 status = "okay";
259};
260
261/* Apalis USBH[2|3|4] */
262&usbh1 {
263 dr_mode = "host";
264 vbus-supply = <&reg_usb_host_vbus>;
265 status = "okay";
266};
267
268/* Apalis USBO1 */
269&usbotg {
270 dr_mode = "host";
271 vbus-supply = <&reg_usb_otg_vbus>;
272 status = "okay";
273};
274
275/* Apalis MMC1 */
276&usdhc1 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
279 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */
280 disable-wp;
281 no-1-8-v;
282 status = "okay";
283};
284
285/* Apalis SD1 */
286&usdhc2 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
289 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* SD1_CD */
290 disable-wp;
291 no-1-8-v;
292 status = "okay";
293};
294
295/* eMMC */
296&usdhc3 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_usdhc3>;
299 vqmmc-supply = <&reg_module_3v3>;
300 bus-width = <8>;
301 no-1-8-v;
302 non-removable;
303 status = "okay";
304};
305
306&iomuxc {
307 pinctrl_apalis_gpio1: gpio2io04grp {
308 fsl,pins = <
309 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
310 >;
311 };
312
313 pinctrl_apalis_gpio2: gpio2io05grp {
314 fsl,pins = <
315 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
316 >;
317 };
318
319 pinctrl_apalis_gpio3: gpio2io06grp {
320 fsl,pins = <
321 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
322 >;
323 };
324
325 pinctrl_apalis_gpio4: gpio2io07grp {
326 fsl,pins = <
327 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
328 >;
329 };
330
331 pinctrl_apalis_gpio5: gpio6io10grp {
332 fsl,pins = <
333 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
334 >;
335 };
336
337 pinctrl_apalis_gpio6: gpio6io09grp {
338 fsl,pins = <
339 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
340 >;
341 };
342
343 pinctrl_apalis_gpio7: gpio1io02grp {
344 fsl,pins = <
345 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
346 >;
347 };
348
349 pinctrl_apalis_gpio8: gpio1io06grp {
350 fsl,pins = <
351 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
352 >;
353 };
354
355 pinctrl_audmux: audmuxgrp {
356 fsl,pins = <
357 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
358 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
359 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
360 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
361 /* SGTL5000 sys_mclk */
362 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
363 >;
364 };
365
366 pinctrl_cam_mclk: cammclkgrp {
367 fsl,pins = <
368 /* CAM sys_mclk */
369 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
370 >;
371 };
372
373 pinctrl_ecspi1: ecspi1grp {
374 fsl,pins = <
375 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
376 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
377 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
378 /* SPI1 cs */
379 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
380 >;
381 };
382
383 pinctrl_ecspi2: ecspi2grp {
384 fsl,pins = <
385 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
386 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
387 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
388 /* SPI2 cs */
389 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
390 >;
391 };
392
393 pinctrl_enet: enetgrp {
394 fsl,pins = <
395 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
396 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
397 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
398 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
399 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
400 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
401 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
402 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
403 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
404 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
405 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
406 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
407 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
408 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
409 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
410 /* Ethernet PHY reset */
411 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
412 /* Ethernet PHY interrupt */
413 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
414 >;
415 };
416
417 pinctrl_flexcan1: flexcan1grp {
418 fsl,pins = <
419 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
420 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
421 >;
422 };
423
424 pinctrl_flexcan2: flexcan2grp {
425 fsl,pins = <
426 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
427 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
428 >;
429 };
430
431 pinctrl_gpio_bl_on: gpioblon {
432 fsl,pins = <
433 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
434 >;
435 };
436
437 pinctrl_gpio_keys: gpio1io04grp {
438 fsl,pins = <
439 /* Power button */
440 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
441 >;
442 };
443
444 pinctrl_hdmi_cec: hdmicecgrp {
445 fsl,pins = <
446 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
447 >;
448 };
449
450 pinctrl_hdmi_ddc: hdmiddcgrp {
451 fsl,pins = <
452 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
453 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
454 >;
455 };
456
457 pinctrl_i2c1: i2c1grp {
458 fsl,pins = <
459 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
460 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
461 >;
462 };
463
464 pinctrl_i2c2: i2c2grp {
465 fsl,pins = <
466 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
467 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
468 >;
469 };
470
471 pinctrl_i2c3: i2c3grp {
472 fsl,pins = <
473 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
474 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
475 >;
476 };
477
478 pinctrl_i2c3_recovery: i2c3recoverygrp {
479 fsl,pins = <
480 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
481 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
482 >;
483 };
484
485 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
486 fsl,pins = <
487 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
488 /* DE */
489 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
490 /* HSync */
491 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
492 /* VSync */
493 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
494 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
495 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
496 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
497 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
498 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
499 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
500 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
501 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
502 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
503 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
504 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
505 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
506 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
507 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
508 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
509 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
510 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
511 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
512 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
513 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
514 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
515 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
516 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
517 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
518 >;
519 };
520
521 pinctrl_ipu2_vdac: ipu2vdacgrp {
522 fsl,pins = <
523 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
524 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
525 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
526 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
527 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
528 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
529 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
530 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
531 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
532 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
533 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
534 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
535 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
536 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
537 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
538 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
539 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
540 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
541 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
542 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
543 >;
544 };
545
546 pinctrl_mmc_cd: gpiommccdgrp {
547 fsl,pins = <
548 /* MMC1 CD */
549 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
550 >;
551 };
552
553 pinctrl_pwm1: pwm1grp {
554 fsl,pins = <
555 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
556 >;
557 };
558
559 pinctrl_pwm2: pwm2grp {
560 fsl,pins = <
561 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
562 >;
563 };
564
565 pinctrl_pwm3: pwm3grp {
566 fsl,pins = <
567 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
568 >;
569 };
570
571 pinctrl_pwm4: pwm4grp {
572 fsl,pins = <
573 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
574 >;
575 };
576
577 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
578 fsl,pins = <
579 /* USBH_EN */
580 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
581 >;
582 };
583
584 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
585 fsl,pins = <
586 /* USBH_HUB_EN */
587 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
588 >;
589 };
590
591 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
592 fsl,pins = <
593 /* USBO1 power en */
594 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
595 >;
596 };
597
598 pinctrl_reset_moci: gpioresetmocigrp {
599 fsl,pins = <
600 /* RESET_MOCI control */
601 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
602 >;
603 };
604
605 pinctrl_sd_cd: gpiosdcdgrp {
606 fsl,pins = <
607 /* SD1 CD */
608 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
609 >;
610 };
611
612 pinctrl_spdif: spdifgrp {
613 fsl,pins = <
614 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
615 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
616 >;
617 };
618
619 pinctrl_touch_int: gpiotouchintgrp {
620 fsl,pins = <
621 /* STMPE811 interrupt */
622 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
623 >;
624 };
625
626 pinctrl_uart1_dce: uart1dcegrp {
627 fsl,pins = <
628 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
629 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
630 >;
631 };
632
633 /* DTE mode */
634 pinctrl_uart1_dte: uart1dtegrp {
635 fsl,pins = <
636 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
637 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
638 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
639 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
640 >;
641 };
642
643 /* Additional DTR, DSR, DCD */
644 pinctrl_uart1_ctrl: uart1ctrlgrp {
645 fsl,pins = <
646 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
647 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
648 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
649 >;
650 };
651
652 pinctrl_uart2_dce: uart2dcegrp {
653 fsl,pins = <
654 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
655 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
656 >;
657 };
658
659 /* DTE mode */
660 pinctrl_uart2_dte: uart2dtegrp {
661 fsl,pins = <
662 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
663 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
664 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
665 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
666 >;
667 };
668
669 pinctrl_uart4_dce: uart4dcegrp {
670 fsl,pins = <
671 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
672 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
673 >;
674 };
675
676 /* DTE mode */
677 pinctrl_uart4_dte: uart4dtegrp {
678 fsl,pins = <
679 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
680 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
681 >;
682 };
683
684 pinctrl_uart5_dce: uart5dcegrp {
685 fsl,pins = <
686 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
687 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
688 >;
689 };
690
691 /* DTE mode */
692 pinctrl_uart5_dte: uart5dtegrp {
693 fsl,pins = <
694 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
695 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
696 >;
697 };
698
699 pinctrl_usbotg: usbotggrp {
700 fsl,pins = <
701 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
702 >;
703 };
704
705 pinctrl_usdhc1_4bit: usdhc1grp_4bit {
706 fsl,pins = <
707 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
708 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
709 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
710 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
711 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
712 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
713 >;
714 };
715
716 pinctrl_usdhc1_8bit: usdhc1grp_8bit {
717 fsl,pins = <
718 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
719 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
720 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
721 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
722 >;
723 };
724
725 pinctrl_usdhc2: usdhc2grp {
726 fsl,pins = <
727 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
728 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
729 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
730 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
731 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
732 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
733 >;
734 };
735
736 pinctrl_usdhc3: usdhc3grp {
737 fsl,pins = <
738 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
739 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
740 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
741 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
742 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
743 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
744 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
745 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
746 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
747 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
748 /* eMMC reset */
749 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
750 >;
751 };
752};