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git01.mediatek.com / filogic / uboot / 824946c6ccbb3f520df37b9ee2766447b36ec3ff / . / arch / xtensa / include / asm / arch-de212 / tie-asm.h
blob: 5156aae71e3834862aa216bcebaeebd4b8695cdb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Max Filippov49739402016-08-10 18:36:47 +0300[diff] [blame]2/*
3 * This header file contains assembly-language definitions (assembly
4 * macros, etc.) for this specific Xtensa processor's TIE extensions
5 * and options. It is customized to this Xtensa processor configuration.
6 * This file is autogenerated, please do not edit.
7 *
8 * Copyright (C) 1999-2015 Cadence Design Systems Inc.
Max Filippov49739402016-08-10 18:36:47 +0300[diff] [blame]9 */
10
11#ifndef _XTENSA_CORE_TIE_ASM_H
12#define _XTENSA_CORE_TIE_ASM_H
13
14/* Selection parameter values for save-area save/restore macros: */
15/* Option vs. TIE: */
16#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
18#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
19/* Whether used automatically by compiler: */
20#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
21#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
22#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
28/* Misc */
29#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
30#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
31 | ((ccuse) & XTHAL_SAS_ANYCC) \
32 | ((abi) & XTHAL_SAS_ANYABI) )
33
Max Filippov49739402016-08-10 18:36:47 +0300[diff] [blame]34 /*
35 * Macro to store all non-coprocessor (extra) custom TIE and optional state
36 * (not including zero-overhead loop registers).
37 * Required parameters:
38 * ptr Save area pointer address register (clobbered)
39 * (register must contain a 4 byte aligned address).
40 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
41 * registers are clobbered, the remaining are unused).
42 * Optional parameters:
43 * continue If macro invoked as part of a larger store sequence, set to 1
44 * if this is not the first in the sequence. Defaults to 0.
45 * ofs Offset from start of larger sequence (from value of first ptr
46 * in sequence) at which to store. Defaults to next available space
47 * (or 0 if <continue> is 0).
48 * select Select what category(ies) of registers to store, as a bitmask
49 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
50 * alloc Select what category(ies) of registers to allocate; if any
51 * category is selected here that is not in <select>, space for
52 * the corresponding registers is skipped without doing any store.
53 */
54 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
55 xchal_sa_start \continue, \ofs
56 // Optional caller-saved registers used by default by the compiler:
57 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
58 xchal_sa_align \ptr, 0, 1016, 4, 4
59 rsr.ACCLO \at1 // MAC16 option
60 s32i \at1, \ptr, .Lxchal_ofs_+0
61 rsr.ACCHI \at1 // MAC16 option
62 s32i \at1, \ptr, .Lxchal_ofs_+4
63 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
64 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
65 xchal_sa_align \ptr, 0, 1016, 4, 4
66 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
67 .endif
68 // Optional caller-saved registers not used by default by the compiler:
69 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
70 xchal_sa_align \ptr, 0, 1004, 4, 4
71 rsr.SCOMPARE1 \at1 // conditional store option
72 s32i \at1, \ptr, .Lxchal_ofs_+0
73 rsr.M0 \at1 // MAC16 option
74 s32i \at1, \ptr, .Lxchal_ofs_+4
75 rsr.M1 \at1 // MAC16 option
76 s32i \at1, \ptr, .Lxchal_ofs_+8
77 rsr.M2 \at1 // MAC16 option
78 s32i \at1, \ptr, .Lxchal_ofs_+12
79 rsr.M3 \at1 // MAC16 option
80 s32i \at1, \ptr, .Lxchal_ofs_+16
81 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
82 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
83 xchal_sa_align \ptr, 0, 1004, 4, 4
84 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
85 .endif
86 .endm // xchal_ncp_store
87
88 /*
89 * Macro to load all non-coprocessor (extra) custom TIE and optional state
90 * (not including zero-overhead loop registers).
91 * Required parameters:
92 * ptr Save area pointer address register (clobbered)
93 * (register must contain a 4 byte aligned address).
94 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
95 * registers are clobbered, the remaining are unused).
96 * Optional parameters:
97 * continue If macro invoked as part of a larger load sequence, set to 1
98 * if this is not the first in the sequence. Defaults to 0.
99 * ofs Offset from start of larger sequence (from value of first ptr
100 * in sequence) at which to load. Defaults to next available space
101 * (or 0 if <continue> is 0).
102 * select Select what category(ies) of registers to load, as a bitmask
103 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
104 * alloc Select what category(ies) of registers to allocate; if any
105 * category is selected here that is not in <select>, space for
106 * the corresponding registers is skipped without doing any load.
107 */
108 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
109 xchal_sa_start \continue, \ofs
110 // Optional caller-saved registers used by default by the compiler:
111 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
112 xchal_sa_align \ptr, 0, 1016, 4, 4
113 l32i \at1, \ptr, .Lxchal_ofs_+0
114 wsr.ACCLO \at1 // MAC16 option
115 l32i \at1, \ptr, .Lxchal_ofs_+4
116 wsr.ACCHI \at1 // MAC16 option
117 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
118 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
119 xchal_sa_align \ptr, 0, 1016, 4, 4
120 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
121 .endif
122 // Optional caller-saved registers not used by default by the compiler:
123 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
124 xchal_sa_align \ptr, 0, 1004, 4, 4
125 l32i \at1, \ptr, .Lxchal_ofs_+0
126 wsr.SCOMPARE1 \at1 // conditional store option
127 l32i \at1, \ptr, .Lxchal_ofs_+4
128 wsr.M0 \at1 // MAC16 option
129 l32i \at1, \ptr, .Lxchal_ofs_+8
130 wsr.M1 \at1 // MAC16 option
131 l32i \at1, \ptr, .Lxchal_ofs_+12
132 wsr.M2 \at1 // MAC16 option
133 l32i \at1, \ptr, .Lxchal_ofs_+16
134 wsr.M3 \at1 // MAC16 option
135 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
136 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
137 xchal_sa_align \ptr, 0, 1004, 4, 4
138 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
139 .endif
140 .endm // xchal_ncp_load
141
Max Filippov49739402016-08-10 18:36:47 +0300[diff] [blame]142#define XCHAL_NCP_NUM_ATMPS 1
143
144#define XCHAL_SA_NUM_ATMPS 1
145
146#endif /*_XTENSA_CORE_TIE_ASM_H*/