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git01.mediatek.com / filogic / uboot / 8226dfdaeb450e7e5c8a18100f5b64c74563a9ce / . / arch / arm / lib / asm-offsets.c
blob: b0c26e5d689318195343152926eac50699cdd3d7 [file] [log] [blame]
Masahiro Yamada8226dfd2014-03-18 16:38:13 +0900[diff] [blame^]1/*
2 * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3 *
4 * This program is used to generate definitions needed by
5 * assembly language modules.
6 *
7 * We use the technique used in the OSF Mach kernel code:
8 * generate asm statements containing #defines,
9 * compile this file to assembler, and then extract the
10 * #defines from the assembly-language output.
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#include <common.h>
16#include <linux/kbuild.h>
17
18#if defined(CONFIG_MB86R0x)
19#include <asm/arch/mb86r0x.h>
20#endif
21#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
22 || defined(CONFIG_MX51) || defined(CONFIG_MX53)
23#include <asm/arch/imx-regs.h>
24#endif
25
26int main(void)
27{
28 /*
29 * TODO : Check if each entry in this file is really necessary.
30 * - struct mb86r0x_ddr2
31 * - struct mb86r0x_memc
32 * - struct esdramc_regs
33 * - struct max_regs
34 * - struct aips_regs
35 * - struct aipi_regs
36 * - struct clkctl
37 * - struct dpll
38 * are used only for generating asm-offsets.h.
39 * It means their offset addresses are referenced only from assembly
40 * code. Is it better to define the macros directly in headers?
41 */
42
43#if defined(CONFIG_MB86R0x)
44 /* ddr2 controller */
45 DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
46 DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
47 DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
48 DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
49 DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
50 DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
51 DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
52 DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
53 DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
54 DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
55 DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
56 DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
57 DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
58 DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
59 DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
60
61 /* clock reset generator */
62 DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
63 DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
64 DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
65 DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
66 DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
67 DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
68
69 /* chip control module */
70 DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
71
72 /* external bus interface */
73 DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
74 DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
75 DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
76 DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
77 DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
78 DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
79 DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
80 DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
81 DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
82#endif
83
84#if defined(CONFIG_MX25)
85 /* Clock Control Module */
86 DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
87 DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
88 DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
89 DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
90 DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
91 DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
92
93 /* Enhanced SDRAM Controller */
94 DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
95 DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
96 DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
97
98 /* Multi-Layer AHB Crossbar Switch */
99 DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
100 DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
101 DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
102 DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
103 DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
104 DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
105 DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
106 DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
107 DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
108 DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
109 DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
110 DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
111 DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
112 DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
113 DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
114
115 /* AHB <-> IP-Bus Interface */
116 DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
117 DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
118#endif
119
120#if defined(CONFIG_MX27)
121 DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
122 DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
123 DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
124 DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
125
126 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
127 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
128 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
129 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
130 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
131 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
132 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
133
134 DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
135 DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
136 DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
137 DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
138 DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
139
140 DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
141 offsetof(struct system_control_regs, gpcr));
142 DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
143 offsetof(struct system_control_regs, fmcr));
144#endif
145
146#if defined(CONFIG_MX35)
147 /* Round up to make sure size gives nice stack alignment */
148 DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
149 DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
150 DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
151 DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
152 DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
153 DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
154 DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
155 DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
156 DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
157 DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
158 DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
159 DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
160 DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
161 DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
162 DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
163
164 /* Multi-Layer AHB Crossbar Switch */
165 DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
166 DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
167 DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
168 DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
169 DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
170 DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
171 DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
172 DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
173 DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
174 DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
175 DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
176 DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
177 DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
178 DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
179 DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
180 DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
181
182 /* AHB <-> IP-Bus Interface */
183 DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
184 DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
185 DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
186 DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
187 DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
188 DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
189 DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
190 DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
191 DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
192 DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
193 DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
194#endif
195
196#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
197 /* Round up to make sure size gives nice stack alignment */
198 DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
199 DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
200 DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
201 DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
202 DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
203 DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
204 DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
205 DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
206 DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
207 DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
208 DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
209 DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
210 DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
211 DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
212 DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
213 DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
214 DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
215 DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
216 DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
217 DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
218 DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
219 DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
220 DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
221 DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
222 DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
223 DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
224 DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
225 DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
226 DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
227 DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
228 DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
229 DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
230 DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
231 DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
232#if defined(CONFIG_MX53)
233 DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
234#endif
235
236 /* DPLL */
237 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
238 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
239 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
240 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
241 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
242 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
243 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
244 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
245#endif
246
247 return 0;
248}