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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ashish Kumarb25faa22017-08-31 16:12:53 +05302/*
3 * Copyright 2017 NXP
Ashish Kumarb25faa22017-08-31 16:12:53 +05304 */
5
6#include <common.h>
7#include <asm/arch/fsl_serdes.h>
8
9struct serdes_config {
10 u8 ip_protocol;
11 u8 lanes[SRDS_MAX_LANES];
12 u8 rcw_lanes[SRDS_MAX_LANES];
13};
14
15static struct serdes_config serdes1_cfg_tbl[] = {
16 /* SerDes 1 */
17 {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
18 {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
19 {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
20 {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
21 {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
22 {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
23 {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
24 {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
25 {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
26 {0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
27 {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
28 {0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },
29 {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
30 {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
31 {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
32 {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
33 {}
34};
35static struct serdes_config serdes2_cfg_tbl[] = {
36 /* SerDes 2 */
37 {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
38 {0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },
39 {0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },
40 {0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },
41 {0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },
42 {0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },
43 {}
44};
45
46static struct serdes_config *serdes_cfg_tbl[] = {
47 serdes1_cfg_tbl,
48 serdes2_cfg_tbl,
49};
50
51int serdes_get_number(int serdes, int cfg)
52{
53 struct serdes_config *ptr;
54 int i, j, index, lnk;
55 int is_found, max_lane = SRDS_MAX_LANES;
56
57 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
58 return 0;
59
60 ptr = serdes_cfg_tbl[serdes];
61
62 while (ptr->ip_protocol) {
63 is_found = 1;
64 for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
65 lnk = cfg & (0xf << 4 * i);
66 lnk = lnk >> (4 * i);
67
68 index = (serdes == FSL_SRDS_1) ? j : i;
69
70 if (ptr->rcw_lanes[index] == lnk && is_found)
71 is_found = 1;
72 else
73 is_found = 0;
74 }
75
76 if (is_found)
77 return ptr->ip_protocol;
78 ptr++;
79 }
80
81 return 0;
82}
83
84enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
85{
86 struct serdes_config *ptr;
87
88 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
89 return 0;
90
91 ptr = serdes_cfg_tbl[serdes];
92 while (ptr->ip_protocol) {
93 if (ptr->ip_protocol == cfg)
94 return ptr->lanes[lane];
95 ptr++;
96 }
97
98 return 0;
99}
100
101int is_serdes_prtcl_valid(int serdes, u32 prtcl)
102{
103 int i;
104 struct serdes_config *ptr;
105
106 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
107 return 0;
108
109 ptr = serdes_cfg_tbl[serdes];
110 while (ptr->ip_protocol) {
111 if (ptr->ip_protocol == prtcl)
112 break;
113 ptr++;
114 }
115
116 if (!ptr->ip_protocol)
117 return 0;
118
119 for (i = 0; i < SRDS_MAX_LANES; i++) {
120 if (ptr->lanes[i] != NONE)
121 return 1;
122 }
123
124 return 0;
125}