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git01.mediatek.com / filogic / uboot / 82073c0da15db98ae9f33f56c5e09a31ac6e0e80 / . / arch / arm / dts / rk3308-u-boot.dtsi
blob: 684fa7abddb12a5fd0cc15165f779a52d281454c [file] [log] [blame]
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 *(C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Kever Yangd4d2b222020-01-08 17:38:48 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &emmc;
11 mmc1 = &sdmmc;
12 };
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000[diff] [blame]13
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]14 chosen {
15 u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
16 };
17
Jonas Karlmanc8c20092024-04-08 18:14:07 +0000[diff] [blame]18 dmc: dmc@ff010000 {
19 compatible = "rockchip,rk3308-dmc";
20 reg = <0x0 0xff010000 0x0 0x10000>;
21 bootph-all;
22 };
23
Jonas Karlman1cf34dd2024-04-08 18:14:01 +0000[diff] [blame]24 otp: nvmem@ff210000 {
25 compatible = "rockchip,rk3308-otp";
26 reg = <0x0 0xff210000 0x0 0x4000>;
27 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
28 <&cru PCLK_OTP_PHY>;
29 clock-names = "otp", "apb_pclk", "phy";
30 resets = <&cru SRST_OTP_PHY>;
31 reset-names = "phy";
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 cpu_id: id@7 {
36 reg = <0x07 0x10>;
37 };
38 };
Jonas Karlmanfbced692024-04-08 18:14:02 +0000[diff] [blame]39
40 rng: rng@ff2f0000 {
41 compatible = "rockchip,cryptov2-rng";
42 reg = <0x0 0xff2f0000 0x0 0x4000>;
43 };
Kever Yangd4d2b222020-01-08 17:38:48 +0800[diff] [blame]44};
45
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]46&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]48};
49
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]50&emmc {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]51 bootph-pre-ram;
52 bootph-some-ram;
53
Andy Yan134eb022019-11-26 21:15:38 +0800[diff] [blame]54 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
55 u-boot,spl-fifo-mode;
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]56};
57
58&emmc_bus8 {
59 bootph-pre-ram;
60 bootph-some-ram;
61};
62
63&emmc_clk {
64 bootph-pre-ram;
65 bootph-some-ram;
66};
67
68&emmc_cmd {
69 bootph-pre-ram;
70 bootph-some-ram;
71};
72
73&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]75};
76
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]77&pcfg_pull_none {
Pegorer Massimof8cc29b2023-07-15 10:19:40 +0000[diff] [blame]78 bootph-all;
Pegorer Massimof8cc29b2023-07-15 10:19:40 +0000[diff] [blame]79};
80
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]81&pcfg_pull_none_4ma {
82 bootph-pre-ram;
83 bootph-some-ram;
84};
85
86&pcfg_pull_none_8ma {
87 bootph-pre-ram;
88 bootph-some-ram;
89};
90
91&pcfg_pull_up {
92 bootph-all;
93};
94
95&pcfg_pull_up_4ma {
96 bootph-pre-ram;
97 bootph-some-ram;
98};
99
100&pcfg_pull_up_8ma {
101 bootph-pre-ram;
102 bootph-some-ram;
103};
104
105&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-all;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]107};
108
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]109&rtc_32k {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-all;
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]111};
112
113&sdmmc {
114 bootph-pre-ram;
115 bootph-some-ram;
116
117 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
118 u-boot,spl-fifo-mode;
119};
120
121&sdmmc_bus4 {
122 bootph-pre-ram;
123 bootph-some-ram;
124};
125
126&sdmmc_clk {
127 bootph-pre-ram;
128 bootph-some-ram;
129};
130
131&sdmmc_cmd {
132 bootph-pre-ram;
133 bootph-some-ram;
134};
135
136&sdmmc_det {
137 bootph-pre-ram;
138 bootph-some-ram;
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]139};
Jonas Karlmanc8c20092024-04-08 18:14:07 +0000[diff] [blame]140
141&xin24m {
142 bootph-all;
143};