| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <config.h> |
| 8 | #include <command.h> |
| 9 | #include <mpc8xx.h> |
| 10 | #include <version.h> |
| 11 | |
| 12 | #define CONFIG_8xx 1 /* needed for Linux kernel header files */ |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 13 | |
| 14 | #include <ppc_asm.tmpl> |
| 15 | #include <ppc_defs.h> |
| 16 | |
| 17 | #include <asm/cache.h> |
| 18 | #include <asm/mmu.h> |
| 19 | |
| Jon Loeliger | 526e5ce | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 20 | #if defined(CONFIG_CMD_KGDB) |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * cache flushing routines for kgdb |
| 24 | */ |
| 25 | |
| 26 | .globl kgdb_flush_cache_all |
| 27 | kgdb_flush_cache_all: |
| 28 | lis r3, IDC_INVALL@h |
| 29 | mtspr DC_CST, r3 |
| 30 | sync |
| 31 | lis r3, IDC_INVALL@h |
| 32 | mtspr IC_CST, r3 |
| 33 | SYNC |
| 34 | blr |
| 35 | |
| 36 | .globl kgdb_flush_cache_range |
| 37 | kgdb_flush_cache_range: |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | li r5,CONFIG_SYS_CACHELINE_SIZE-1 |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 39 | andc r3,r3,r5 |
| 40 | subf r4,r3,r4 |
| 41 | add r4,r4,r5 |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 43 | beqlr |
| 44 | mtctr r4 |
| 45 | mr r6,r3 |
| 46 | 1: dcbst 0,r3 |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 48 | bdnz 1b |
| 49 | sync /* wait for dcbst's to get to ram */ |
| 50 | mtctr r4 |
| 51 | 2: icbi 0,r6 |
| Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | addi r6,r6,CONFIG_SYS_CACHELINE_SIZE |
| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 53 | bdnz 2b |
| 54 | SYNC |
| 55 | blr |
| 56 | |
| Jon Loeliger | 07efe2a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 57 | #endif |