blob: 46c9207a93bb54559e37cf79e4457234eca7c601 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiewb859ef12007-08-16 19:23:50 -05002/*
3 *
Alison Wangd132fe62012-03-26 21:49:06 +00004 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewb859ef12007-08-16 19:23:50 -05005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewb859ef12007-08-16 19:23:50 -05006 */
7
8/* CPU specific interrupt routine */
Simon Glass9b61c7c2019-11-14 12:57:41 -07009#include <irq_func.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -050010#include <asm/immap.h>
Alison Wangd132fe62012-03-26 21:49:06 +000011#include <asm/io.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -050012
13int interrupt_init(void)
14{
Tom Rini364d0022023-01-10 11:19:45 -050015 int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050016
17 /* Make sure all interrupts are disabled */
Alison Wangd132fe62012-03-26 21:49:06 +000018 setbits_be32(&intp->imrl0, 0x1);
TsiChungLiewb859ef12007-08-16 19:23:50 -050019
20 enable_interrupts();
21 return 0;
22}
23
Marek Vasut38908f52023-03-23 01:20:39 +010024#if CONFIG_IS_ENABLED(MCFTMR)
TsiChungLiewb859ef12007-08-16 19:23:50 -050025void dtimer_intr_setup(void)
26{
Tom Rini364d0022023-01-10 11:19:45 -050027 int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050028
Tom Rini364d0022023-01-10 11:19:45 -050029 out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
Alison Wangd132fe62012-03-26 21:49:06 +000030 clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
Tom Rini364d0022023-01-10 11:19:45 -050031 clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
TsiChungLiewb859ef12007-08-16 19:23:50 -050032}
33#endif