| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef _PINMUX_H_ |
| 25 | #define _PINMUX_H_ |
| 26 | |
| 27 | /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ |
| 28 | struct pmux_tri_ctlr { |
| 29 | uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ |
| 30 | uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ |
| 31 | uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ |
| 32 | uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ |
| 33 | uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ |
| 34 | uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */ |
| 35 | uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */ |
| 36 | uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */ |
| 37 | uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */ |
| 38 | uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ |
| 39 | |
| 40 | uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ |
| 41 | |
| 42 | uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */ |
| 43 | uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */ |
| 44 | uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */ |
| 45 | uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */ |
| 46 | uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */ |
| 47 | uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */ |
| 48 | uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */ |
| 49 | }; |
| 50 | |
| 51 | #define Z_GMC (1 << 29) |
| 52 | #define Z_IRRX (1 << 20) |
| 53 | #define Z_IRTX (1 << 19) |
| 54 | |
| 55 | #endif /* PINMUX_H */ |