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Mike Frysinger94bae5c2008-03-30 15:46:13 -04001/*
2 * serial.h - common serial defines for early debug and serial driver.
3 * any functions defined here must be always_inline since
4 * initcode cannot have function calls.
5 *
6 * Copyright (c) 2004-2007 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#ifndef __BFIN_CPU_SERIAL_H__
12#define __BFIN_CPU_SERIAL_H__
13
14#include <asm/blackfin.h>
15#include <asm/mach-common/bits/uart.h>
16
Mike Frysinger500f2bb2008-10-11 21:52:17 -040017#ifndef CONFIG_UART_CONSOLE
18# define CONFIG_UART_CONSOLE 0
19#endif
20
Mike Frysinger94bae5c2008-03-30 15:46:13 -040021#ifdef CONFIG_DEBUG_EARLY_SERIAL
22# define BFIN_DEBUG_EARLY_SERIAL 1
23#else
24# define BFIN_DEBUG_EARLY_SERIAL 0
25#endif
26
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050027#ifndef __ASSEMBLY__
28
Mike Frysinger94bae5c2008-03-30 15:46:13 -040029#define LOB(x) ((x) & 0xFF)
30#define HIB(x) (((x) >> 8) & 0xFF)
31
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050032/*
33 * All Blackfin system MMRs are padded to 32bits even if the register
34 * itself is only 16bits. So use a helper macro to streamline this.
35 */
36#define __BFP(m) u16 m; u16 __pad_##m
37struct bfin_mmr_serial {
38#ifdef __ADSPBF54x__
39 __BFP(dll);
40 __BFP(dlh);
41 __BFP(gctl);
42 __BFP(lcr);
43 __BFP(mcr);
44 __BFP(lsr);
45 __BFP(msr);
46 __BFP(scr);
47 __BFP(ier_set);
48 __BFP(ier_clear);
49 __BFP(thr);
50 __BFP(rbr);
51#else
52 union {
53 u16 dll;
54 u16 thr;
55 const u16 rbr;
56 };
57 const u16 __spad0;
58 union {
59 u16 dlh;
60 u16 ier;
61 };
62 const u16 __spad1;
63 const __BFP(iir);
64 __BFP(lcr);
65 __BFP(mcr);
66 __BFP(lsr);
67 __BFP(msr);
68 __BFP(scr);
69 const u32 __spad2;
70 __BFP(gctl);
71#endif
72};
73#undef __BFP
74
Mike Frysinger94bae5c2008-03-30 15:46:13 -040075#ifndef UART_LSR
76# if (CONFIG_UART_CONSOLE == 3)
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050077# define UART_BASE UART3_DLL
Mike Frysinger94bae5c2008-03-30 15:46:13 -040078# elif (CONFIG_UART_CONSOLE == 2)
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050079# define UART_BASE UART2_DLL
Mike Frysinger94bae5c2008-03-30 15:46:13 -040080# elif (CONFIG_UART_CONSOLE == 1)
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050081# define UART_BASE UART1_DLL
Mike Frysinger94bae5c2008-03-30 15:46:13 -040082# elif (CONFIG_UART_CONSOLE == 0)
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050083# define UART_BASE UART0_DLL
84# endif
85#else
86# if CONFIG_UART_CONSOLE != 0
87# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
Mike Frysinger94bae5c2008-03-30 15:46:13 -040088# endif
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050089# define UART_BASE UART_DLL
Mike Frysinger94bae5c2008-03-30 15:46:13 -040090#endif
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050091#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE)
Mike Frysinger94bae5c2008-03-30 15:46:13 -040092
Mike Frysinger94bae5c2008-03-30 15:46:13 -040093#ifdef __ADSPBF54x__
94# define ACCESS_LATCH()
95# define ACCESS_PORT_IER()
Mike Frysinger94bae5c2008-03-30 15:46:13 -040096#else
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050097# define ACCESS_LATCH() \
98 bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
99# define ACCESS_PORT_IER() \
100 bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400101#endif
102
103__attribute__((always_inline))
104static inline void serial_do_portmux(void)
105{
Mike Frysinger07374482008-10-11 21:15:53 -0400106#if defined(__ADSPBF51x__)
107# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
108 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
109 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
110 switch (CONFIG_UART_CONSOLE) {
111 case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */
112 case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */
113 }
114 SSYNC();
115#elif defined(__ADSPBF52x__)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400116# define DO_MUX(port, mux, tx, rx) \
117 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
118 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
119 switch (CONFIG_UART_CONSOLE) {
120 case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
121 case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
122 }
123 SSYNC();
124#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
125# define DO_MUX(func, tx, rx) \
126 bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \
127 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx);
128 switch (CONFIG_UART_CONSOLE) {
129 case 0: DO_MUX(PFDE, 0, 1); break;
130 case 1: DO_MUX(PFTE, 2, 3); break;
131 }
132 SSYNC();
133#elif defined(__ADSPBF54x__)
134# define DO_MUX(port, tx, rx) \
135 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
136 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
137 switch (CONFIG_UART_CONSOLE) {
138 case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
139 case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
140 case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
141 case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
142 }
143 SSYNC();
144#endif
145}
146
147__attribute__((always_inline))
148static inline void serial_early_init(void)
149{
150 /* handle portmux crap on different Blackfins */
151 serial_do_portmux();
152
Mike Frysingercad68e12009-04-04 09:10:27 -0400153 /* always enable UART -- avoids anomalies 05000309 and 05000350 */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500154 bfin_write16(&pUART->gctl, UCEN);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400155
156 /* Set LCR to Word Lengh 8-bit word select */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500157 bfin_write16(&pUART->lcr, WLS_8);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400158
159 SSYNC();
160}
161
162__attribute__((always_inline))
Mike Frysinger84451302008-12-10 12:33:54 -0500163static inline void serial_early_put_div(uint16_t divisor)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400164{
Mike Frysinger84451302008-12-10 12:33:54 -0500165 /* Set DLAB in LCR to Access DLL and DLH */
166 ACCESS_LATCH();
167 SSYNC();
168
169 /* Program the divisor to get the baud rate we want */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500170 bfin_write16(&pUART->dll, LOB(divisor));
171 bfin_write16(&pUART->dlh, HIB(divisor));
Mike Frysinger84451302008-12-10 12:33:54 -0500172 SSYNC();
173
174 /* Clear DLAB in LCR to Access THR RBR IER */
175 ACCESS_PORT_IER();
176 SSYNC();
177}
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400178
Mike Frysinger84451302008-12-10 12:33:54 -0500179__attribute__((always_inline))
180static inline uint16_t serial_early_get_div(void)
181{
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400182 /* Set DLAB in LCR to Access DLL and DLH */
183 ACCESS_LATCH();
184 SSYNC();
185
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500186 uint8_t dll = bfin_read16(&pUART->dll);
187 uint8_t dlh = bfin_read16(&pUART->dlh);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400188 uint16_t divisor = (dlh << 8) | dll;
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400189
190 /* Clear DLAB in LCR to Access THR RBR IER */
191 ACCESS_PORT_IER();
192 SSYNC();
193
Mike Frysinger84451302008-12-10 12:33:54 -0500194 return divisor;
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400195}
196
Mike Frysingercca6b792009-04-24 23:54:19 -0400197/* We cannot use get_sclk() early on as it uses caches in external memory */
198#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
199# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
200#endif
201
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400202__attribute__((always_inline))
203static inline void serial_early_set_baud(uint32_t baud)
204{
Mike Frysingerae2d4672008-04-20 03:11:53 -0400205 /* Translate from baud into divisor in terms of SCLK. The
206 * weird multiplication is to make sure we over sample just
207 * a little rather than under sample the incoming signals.
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400208 */
Mike Frysinger84451302008-12-10 12:33:54 -0500209 serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400210}
211
212#ifndef BFIN_IN_INITCODE
213__attribute__((always_inline))
214static inline void serial_early_puts(const char *s)
215{
216 if (BFIN_DEBUG_EARLY_SERIAL) {
217 serial_puts("Early: ");
218 serial_puts(s);
219 }
220}
221#endif
222
223#else
224
225.macro serial_early_init
226#ifdef CONFIG_DEBUG_EARLY_SERIAL
227 call _serial_initialize;
228#endif
229.endm
230
231.macro serial_early_set_baud
232#ifdef CONFIG_DEBUG_EARLY_SERIAL
233 R0.L = LO(CONFIG_BAUDRATE);
234 R0.H = HI(CONFIG_BAUDRATE);
235 call _serial_set_baud;
236#endif
237.endm
238
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400239/* Since we embed the string right into our .text section, we need
240 * to find its address. We do this by getting our PC and adding 2
241 * bytes (which is the length of the jump instruction). Then we
242 * pass this address to serial_puts().
243 */
244#ifdef CONFIG_DEBUG_EARLY_SERIAL
245# define serial_early_puts(str) \
246 call _get_pc; \
247 jump 1f; \
248 .ascii "Early:"; \
249 .ascii __FILE__; \
250 .ascii ": "; \
251 .ascii str; \
252 .asciz "\n"; \
253 .align 4; \
2541: \
255 R0 += 2; \
256 call _serial_puts;
257#else
258# define serial_early_puts(str)
259#endif
260
261#endif
262
263#endif