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Simon Glassd7db0042019-12-08 17:40:16 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Primary-to-Sideband Bridge
4 *
5 * Copyright 2019 Google LLC
6 */
7
8#define LOG_CATEGORY UCLASS_P2SB
9
10#include <common.h>
11#include <dm.h>
12#include <dt-structs.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glassd7db0042019-12-08 17:40:16 -070014#include <p2sb.h>
15#include <spl.h>
16#include <asm/pci.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Simon Glassd7db0042019-12-08 17:40:16 -070018
Simon Glass459a4742020-07-07 21:32:31 -060019#define PCH_P2SB_E0 0xe0
20#define HIDE_BIT BIT(0)
21
Simon Glassd7db0042019-12-08 17:40:16 -070022struct p2sb_platdata {
23#if CONFIG_IS_ENABLED(OF_PLATDATA)
Wolfgang Wallner949a26e2020-02-18 15:32:10 +010024 struct dtd_intel_p2sb dtplat;
Simon Glassd7db0042019-12-08 17:40:16 -070025#endif
26 ulong mmio_base;
27 pci_dev_t bdf;
28};
29
30/* PCI config space registers */
31#define HPTC_OFFSET 0x60
32#define HPTC_ADDR_ENABLE_BIT BIT(7)
33
34/* High Performance Event Timer Configuration */
35#define P2SB_HPTC 0x60
36#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
37
38/*
39 * ADDRESS_SELECT ENCODING_RANGE
40 * 0 0xfed0 0000 - 0xfed0 03ff
41 * 1 0xfed0 1000 - 0xfed0 13ff
42 * 2 0xfed0 2000 - 0xfed0 23ff
43 * 3 0xfed0 3000 - 0xfed0 33ff
44 */
45#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
46#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
47#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
48#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
49
50/*
Wolfgang Wallner949a26e2020-02-18 15:32:10 +010051 * p2sb_early_init() - Enable decoding for HPET range
Simon Glassd7db0042019-12-08 17:40:16 -070052 *
53 * This is needed by FSP-M which uses the High Precision Event Timer.
54 *
55 * @dev: P2SB device
56 * @return 0 if OK, -ve on error
57 */
Wolfgang Wallner949a26e2020-02-18 15:32:10 +010058static int p2sb_early_init(struct udevice *dev)
Simon Glassd7db0042019-12-08 17:40:16 -070059{
60 struct p2sb_platdata *plat = dev_get_platdata(dev);
61 pci_dev_t pdev = plat->bdf;
62
63 /*
64 * Enable decoding for HPET memory address range.
65 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
66 * the High Performance Timer memory address range
67 * selected by bits 1:0
68 */
69 pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
70 PCI_SIZE_8);
71
72 /* Enable PCR Base address in PCH */
73 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
74 PCI_SIZE_32);
75 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
76
77 /* Enable P2SB MSE */
78 pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
79 PCI_COMMAND_MEMORY, PCI_SIZE_8);
80
81 return 0;
82}
83
Wolfgang Wallner949a26e2020-02-18 15:32:10 +010084static int p2sb_spl_init(struct udevice *dev)
Simon Glassd7db0042019-12-08 17:40:16 -070085{
86 /* Enable decoding for HPET. Needed for FSP global pointer storage */
87 dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
88 P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
89
90 return 0;
91}
92
Wolfgang Wallner949a26e2020-02-18 15:32:10 +010093int p2sb_ofdata_to_platdata(struct udevice *dev)
Simon Glassd7db0042019-12-08 17:40:16 -070094{
95 struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
96 struct p2sb_platdata *plat = dev_get_platdata(dev);
97
98#if !CONFIG_IS_ENABLED(OF_PLATDATA)
99 int ret;
Simon Glass9976b012020-04-08 16:57:28 -0600100 u32 base[2];
Simon Glassd7db0042019-12-08 17:40:16 -0700101
Simon Glass9976b012020-04-08 16:57:28 -0600102 ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
103 if (ret)
104 return log_msg_ret("Missing/short early-regs", ret);
105 plat->mmio_base = base[0];
106 /* TPL sets up the initial BAR */
Simon Glassd7db0042019-12-08 17:40:16 -0700107 if (spl_phase() == PHASE_TPL) {
Simon Glassd7db0042019-12-08 17:40:16 -0700108 plat->bdf = pci_get_devfn(dev);
109 if (plat->bdf < 0)
110 return log_msg_ret("Cannot get p2sb PCI address",
111 plat->bdf);
Simon Glassd7db0042019-12-08 17:40:16 -0700112 }
Simon Glass9976b012020-04-08 16:57:28 -0600113 upriv->mmio_base = plat->mmio_base;
Simon Glassd7db0042019-12-08 17:40:16 -0700114#else
115 plat->mmio_base = plat->dtplat.early_regs[0];
116 plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
Simon Glassd7db0042019-12-08 17:40:16 -0700117 upriv->mmio_base = plat->mmio_base;
Simon Glass9976b012020-04-08 16:57:28 -0600118#endif
Simon Glassd7db0042019-12-08 17:40:16 -0700119
120 return 0;
121}
122
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100123static int p2sb_probe(struct udevice *dev)
Simon Glassd7db0042019-12-08 17:40:16 -0700124{
Simon Glass9976b012020-04-08 16:57:28 -0600125 if (spl_phase() == PHASE_TPL)
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100126 return p2sb_early_init(dev);
Simon Glass9976b012020-04-08 16:57:28 -0600127 else if (spl_phase() == PHASE_SPL)
128 return p2sb_spl_init(dev);
Simon Glassd7db0042019-12-08 17:40:16 -0700129
130 return 0;
131}
132
Simon Glass459a4742020-07-07 21:32:31 -0600133static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
134{
135 dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
136 hide ? HIDE_BIT : 0);
137}
138
139static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
140{
141 u16 vendor;
142
143 if (!CONFIG_IS_ENABLED(PCI))
144 return -EPERM;
145 p2sb_set_hide_bit(dev, hide);
146
147 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
148 if (hide && vendor != 0xffff)
149 return log_msg_ret("hide", -EEXIST);
150 else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
151 return log_msg_ret("unhide", -ENOMEDIUM);
152
153 return 0;
154}
155
Simon Glass8719dcc2020-07-07 21:32:32 -0600156static int p2sb_remove(struct udevice *dev)
157{
158 int ret;
159
160 ret = intel_p2sb_set_hide(dev, true);
161 if (ret)
162 return log_msg_ret("hide", ret);
163
164 return 0;
165}
166
Simon Glassd7db0042019-12-08 17:40:16 -0700167static int p2sb_child_post_bind(struct udevice *dev)
168{
169#if !CONFIG_IS_ENABLED(OF_PLATDATA)
170 struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
171 int ret;
172 u32 pid;
173
174 ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
175 if (ret)
176 return ret;
177 pplat->pid = pid;
178#endif
179
180 return 0;
181}
182
Simon Glass459a4742020-07-07 21:32:31 -0600183struct p2sb_ops p2sb_ops = {
184 .set_hide = intel_p2sb_set_hide,
185};
186
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100187static const struct udevice_id p2sb_ids[] = {
188 { .compatible = "intel,p2sb" },
Simon Glassd7db0042019-12-08 17:40:16 -0700189 { }
190};
191
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100192U_BOOT_DRIVER(p2sb_drv) = {
193 .name = "intel_p2sb",
Simon Glassd7db0042019-12-08 17:40:16 -0700194 .id = UCLASS_P2SB,
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100195 .of_match = p2sb_ids,
196 .probe = p2sb_probe,
Simon Glass8719dcc2020-07-07 21:32:32 -0600197 .remove = p2sb_remove,
Simon Glass459a4742020-07-07 21:32:31 -0600198 .ops = &p2sb_ops,
Wolfgang Wallner949a26e2020-02-18 15:32:10 +0100199 .ofdata_to_platdata = p2sb_ofdata_to_platdata,
Simon Glassd7db0042019-12-08 17:40:16 -0700200 .platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
201 .per_child_platdata_auto_alloc_size =
202 sizeof(struct p2sb_child_platdata),
203 .child_post_bind = p2sb_child_post_bind,
Simon Glass8719dcc2020-07-07 21:32:32 -0600204 .flags = DM_FLAG_OS_PREPARE,
Simon Glassd7db0042019-12-08 17:40:16 -0700205};