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git01.mediatek.com / filogic / uboot / 81526d57fb5da8f928dd2d61df4cae6415cfb139 / . / arch / arm / mach-omap2 / omap5 / abb.c
blob: 2f9f8e65d03e6f11b503f855fc303a0e5cca3ff1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]2/*
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]3 * Adaptive Body Bias programming sequence for OMAP5 family
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/omap_common.h>
13#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]15
16/*
17 * Setup LDOVBB for OMAP5.
18 * On OMAP5+ some ABB settings are fused. They are handled
19 * in the following way:
20 *
21 * 1. corresponding EFUSE register contains ABB enable bit
22 * and VSET value
23 * 2. If ABB enable bit is set to 1, than ABB should be
24 * enabled, otherwise ABB should be disabled
25 * 3. If ABB is enabled, than VSET value should be copied
26 * to corresponding MUX control register
27 */
28s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
29{
30 u32 vset;
Nishanth Menon159a21f2017-08-04 21:42:09 -0500[diff] [blame]31 u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK;
32 u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK;
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]33
Nishanth Menon22737ab2014-01-14 12:27:29 -0600[diff] [blame]34 if (!is_omap54xx()) {
35 /* DRA7 */
36 fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
37 fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
38 }
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]39 /*
40 * ABB parameters must be properly fused
41 * otherwise ABB should be disabled
42 */
43 vset = readl(fuse);
Nishanth Menon22737ab2014-01-14 12:27:29 -0600[diff] [blame]44 if (!(vset & fuse_enable_mask))
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]45 return -1;
46
47 /* prepare VSET value for LDOVBB mux register */
Nishanth Menon22737ab2014-01-14 12:27:29 -0600[diff] [blame]48 vset &= fuse_vset_mask;
49 vset >>= ffs(fuse_vset_mask) - 1;
Andrii Tseglytskyi28095da2013-05-20 22:42:08 +0000[diff] [blame]50 vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
51 vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
52
53 /* setup LDOVBB using fused value */
54 clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
55
56 return 0;
57}