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git01.mediatek.com / filogic / uboot / 81526d57fb5da8f928dd2d61df4cae6415cfb139 / . / arch / arm / include / asm / arch-octeontx2 / board.h
blob: 1c9ec113ca55c4d43687b4d05b49d030075dc210 [file] [log] [blame]
Suneel Garapati81526d52019-10-19 18:35:54 -0700[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8#ifndef __BOARD_H__
9#define __BOARD_H__
10
11#include <asm/arch/soc.h>
12
13/** Reg offsets */
14#define RST_BOOT 0x87E006001600ULL
15
16#define CPC_BOOT_OWNERX(a) 0x86D000000160ULL + (8 * (a))
17
18/** Structure definitions */
19/**
20 * Register (NCB32b) cpc_boot_owner#
21 *
22 * CPC Boot Owner Registers These registers control an external arbiter
23 * for the boot device (SPI/eMMC) across multiple external devices. There
24 * is a register for each requester: _ \<0\> - SCP - reset on
25 * SCP reset _ \<1\> - MCP - reset on MCP reset _ \<2\> - AP
26 * Secure - reset on core reset _ \<3\> - AP Nonsecure - reset on core
27 * reset These register is only writable to the corresponding
28 * requestor(s) permitted with CPC_PERMIT.
29 */
30union cpc_boot_ownerx {
31 u32 u;
32 struct cpc_boot_ownerx_s {
33 u32 boot_req : 1;
34 u32 reserved_1_7 : 7;
35 u32 boot_wait : 1;
36 u32 reserved_9_31 : 23;
37 } s;
38};
39
40/**
41 * Register (RSL) rst_boot
42 *
43 * RST Boot Register This register is not accessible through ROM scripts;
44 * see SCR_WRITE32_S[ADDR].
45 */
46union rst_boot {
47 u64 u;
48 struct rst_boot_s {
49 u64 rboot_pin : 1;
50 u64 rboot : 1;
51 u64 reserved_2_32 : 31;
52 u64 pnr_mul : 6;
53 u64 reserved_39 : 1;
54 u64 c_mul : 7;
55 u64 reserved_47_52 : 6;
56 u64 gpio_ejtag : 1;
57 u64 mcp_jtagdis : 1;
58 u64 dis_scan : 1;
59 u64 dis_huk : 1;
60 u64 vrm_err : 1;
61 u64 jt_tstmode : 1;
62 u64 ckill_ppdis : 1;
63 u64 trusted_mode : 1;
64 u64 reserved_61_62 : 2;
65 u64 chipkill : 1;
66 } s;
67 struct rst_boot_cn96xx {
68 u64 rboot_pin : 1;
69 u64 rboot : 1;
70 u64 reserved_2_23 : 22;
71 u64 cpt_mul : 7;
72 u64 reserved_31_32 : 2;
73 u64 pnr_mul : 6;
74 u64 reserved_39 : 1;
75 u64 c_mul : 7;
76 u64 reserved_47_52 : 6;
77 u64 gpio_ejtag : 1;
78 u64 mcp_jtagdis : 1;
79 u64 dis_scan : 1;
80 u64 dis_huk : 1;
81 u64 vrm_err : 1;
82 u64 reserved_58_59 : 2;
83 u64 trusted_mode : 1;
84 u64 scp_jtagdis : 1;
85 u64 jtagdis : 1;
86 u64 chipkill : 1;
87 } cn96xx;
88 struct rst_boot_cnf95xx {
89 u64 rboot_pin : 1;
90 u64 rboot : 1;
91 u64 reserved_2_7 : 6;
92 u64 bphy_mul : 7;
93 u64 reserved_15 : 1;
94 u64 dsp_mul : 7;
95 u64 reserved_23 : 1;
96 u64 cpt_mul : 7;
97 u64 reserved_31_32 : 2;
98 u64 pnr_mul : 6;
99 u64 reserved_39 : 1;
100 u64 c_mul : 7;
101 u64 reserved_47_52 : 6;
102 u64 gpio_ejtag : 1;
103 u64 mcp_jtagdis : 1;
104 u64 dis_scan : 1;
105 u64 dis_huk : 1;
106 u64 vrm_err : 1;
107 u64 reserved_58_59 : 2;
108 u64 trusted_mode : 1;
109 u64 scp_jtagdis : 1;
110 u64 jtagdis : 1;
111 u64 chipkill : 1;
112 } cnf95xx;
113};
114
115extern unsigned long fdt_base_addr;
116
117/** Function definitions */
118void mem_map_fill(void);
119int fdt_get_board_mac_cnt(void);
120u64 fdt_get_board_mac_addr(void);
121const char *fdt_get_board_model(void);
122const char *fdt_get_board_serial(void);
123const char *fdt_get_board_revision(void);
124void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr);
125void board_acquire_flash_arb(bool acquire);
126void cgx_intf_shutdown(void);
127
128#endif /* __BOARD_H__ */