| Ying-Chun Liu (PaulLiu) | e612f68 | 2021-11-05 17:13:24 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright 2021 Linaro |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | /plugin/; |
| 8 | |
| 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | |
| 11 | #include "imx8mm-pinfunc.h" |
| 12 | |
| 13 | &ecspi1 { |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <0>; |
| 16 | fsl,spi-num-chipselects = <1>; |
| 17 | pinctrl-names = "default"; |
| 18 | pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; |
| 19 | cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| 20 | status = "okay"; |
| 21 | }; |
| 22 | |
| 23 | &ecspi2 { |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <0>; |
| 26 | fsl,spi-num-chipselects = <1>; |
| 27 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; |
| 29 | cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; |
| 30 | status = "okay"; |
| 31 | }; |
| 32 | |
| 33 | &ecspi3 { |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <0>; |
| 36 | fsl,spi-num-chipselects = <1>; |
| 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; |
| 39 | cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; |
| 40 | status = "okay"; |
| 41 | }; |
| 42 | |
| 43 | &iomuxc { |
| 44 | pinctrl_ecspi1: ecspi1grp { |
| 45 | fsl,pins = < |
| 46 | MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 |
| 47 | MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 |
| 48 | MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 |
| 49 | >; |
| 50 | }; |
| 51 | |
| 52 | pinctrl_ecspi1_cs: ecspi1cs { |
| 53 | fsl,pins = < |
| 54 | MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 |
| 55 | >; |
| 56 | }; |
| 57 | |
| 58 | pinctrl_ecspi2: ecspi2grp { |
| 59 | fsl,pins = < |
| 60 | MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x02 |
| 61 | MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x02 |
| 62 | MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x102 |
| 63 | >; |
| 64 | }; |
| 65 | |
| 66 | pinctrl_ecspi2_cs: ecspi2_csgrp { |
| 67 | fsl,pins = < |
| 68 | MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 |
| 69 | >; |
| 70 | }; |
| 71 | |
| 72 | pinctrl_ecspi3: ecspi3grp { |
| 73 | fsl,pins = < |
| 74 | MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x02 |
| 75 | MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x02 |
| 76 | MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x102 |
| 77 | >; |
| 78 | }; |
| 79 | |
| 80 | pinctrl_ecspi3_cs: ecspi3_csgrp { |
| 81 | fsl,pins = < |
| 82 | MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000 |
| 83 | >; |
| 84 | }; |
| 85 | }; |