Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 2 | /* |
Kumar Gala | 365024c | 2011-01-31 15:51:20 -0600 | [diff] [blame] | 3 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <command.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 8 | #include <env.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 9 | #include <image.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 12 | #include <net.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 13 | #include <pci.h> |
| 14 | #include <asm/processor.h> |
| 15 | #include <asm/mmu.h> |
Kumar Gala | f81f89f | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 16 | #include <asm/cache.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 17 | #include <asm/immap_85xx.h> |
Kumar Gala | 9bbd643 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 18 | #include <asm/fsl_pci.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 19 | #include <fsl_ddr_sdram.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 20 | #include <asm/io.h> |
Kumar Gala | 3d02038 | 2010-12-15 04:55:20 -0600 | [diff] [blame] | 21 | #include <asm/fsl_serdes.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 22 | #include <miiphy.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 23 | #include <linux/delay.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 24 | #include <linux/libfdt.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 25 | #include <fdt_support.h> |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 26 | #include <tsec.h> |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 27 | #include <fsl_mdio.h> |
Kumar Gala | d3b1b66 | 2009-08-08 10:42:30 -0500 | [diff] [blame] | 28 | #include <netdev.h> |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 29 | |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 30 | #include "../common/sgmii_riser.h" |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 31 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 32 | int checkboard (void) |
| 33 | { |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 34 | u8 vboot; |
| 35 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 36 | |
Timur Tabi | 56953ee | 2012-03-15 11:42:27 +0000 | [diff] [blame] | 37 | printf("Board: MPC8572DS Sys ID: 0x%02x, " |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 38 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
| 39 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
| 40 | in_8(pixis_base + PIXIS_PVER)); |
| 41 | |
| 42 | vboot = in_8(pixis_base + PIXIS_VBOOT); |
| 43 | switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { |
| 44 | case PIXIS_VBOOT_LBMAP_NOR0: |
| 45 | puts ("vBank: 0\n"); |
| 46 | break; |
| 47 | case PIXIS_VBOOT_LBMAP_PJET: |
| 48 | puts ("Promjet\n"); |
| 49 | break; |
| 50 | case PIXIS_VBOOT_LBMAP_NAND: |
| 51 | puts ("NAND\n"); |
| 52 | break; |
| 53 | case PIXIS_VBOOT_LBMAP_NOR1: |
| 54 | puts ("vBank: 1\n"); |
| 55 | break; |
| 56 | } |
| 57 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 58 | return 0; |
| 59 | } |
| 60 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 61 | |
| 62 | #if !defined(CONFIG_SPD_EEPROM) |
| 63 | /* |
| 64 | * Fixed sdram init -- doesn't use serial presence detect. |
| 65 | */ |
| 66 | |
| 67 | phys_size_t fixed_sdram (void) |
| 68 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 70 | struct ccsr_ddr __iomem *ddr = &immap->im_ddr; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 71 | uint d_init; |
| 72 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 74 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 75 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 77 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 78 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 79 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 80 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
| 81 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 82 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 83 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 84 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 85 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 86 | |
| 87 | #if defined (CONFIG_DDR_ECC) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; |
| 89 | ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; |
| 90 | ddr->err_sbe = CONFIG_SYS_DDR_SBE; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 91 | #endif |
| 92 | asm("sync;isync"); |
| 93 | |
| 94 | udelay(500); |
| 95 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 97 | |
| 98 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 99 | d_init = 1; |
| 100 | debug("DDR - 1st controller: memory initializing\n"); |
| 101 | /* |
| 102 | * Poll until memory is initialized. |
| 103 | * 512 Meg at 400 might hit this 200 times or so. |
| 104 | */ |
| 105 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { |
| 106 | udelay(1000); |
| 107 | } |
| 108 | debug("DDR: memory initialized\n\n"); |
| 109 | asm("sync; isync"); |
| 110 | udelay(500); |
| 111 | #endif |
| 112 | |
| 113 | return 512 * 1024 * 1024; |
| 114 | } |
| 115 | |
| 116 | #endif |
| 117 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 118 | #ifdef CONFIG_PCI |
| 119 | void pci_init_board(void) |
| 120 | { |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 121 | struct pci_controller *hose; |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 122 | |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 123 | fsl_pcie_init_board(0); |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 124 | |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 125 | hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 126 | |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 127 | if (hose) { |
| 128 | u32 temp32; |
| 129 | u8 uli_busno = hose->first_busno + 2; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 130 | |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 131 | /* |
| 132 | * Activate ULI1575 legacy chip by performing a fake |
| 133 | * memory access. Needed to make ULI RTC work. |
| 134 | * Device 1d has the first on-board memory BAR. |
| 135 | */ |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 136 | pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 137 | PCI_BASE_ADDRESS_1, &temp32); |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 138 | |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 139 | if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 140 | void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), |
Kumar Gala | fd19d1e | 2009-09-03 10:20:09 -0500 | [diff] [blame] | 141 | temp32, 4, 0); |
| 142 | debug(" uli1572 read to %p\n", p); |
| 143 | in_be32(p); |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 144 | } |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 145 | } |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 146 | } |
| 147 | #endif |
| 148 | |
| 149 | int board_early_init_r(void) |
| 150 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 152 | int flash_esel = find_tlb_idx((void *)flashbase, 1); |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * Remap Boot flash + PROMJET region to caching-inhibited |
| 156 | * so that flash can be erased properly. |
| 157 | */ |
| 158 | |
Kumar Gala | f81f89f | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 159 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 160 | flush_dcache(); |
| 161 | invalidate_icache(); |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 162 | |
York Sun | 220c346 | 2014-06-24 21:16:20 -0700 | [diff] [blame] | 163 | if (flash_esel == -1) { |
| 164 | /* very unlikely unless something is messed up */ |
| 165 | puts("Error: Could not find TLB for FLASH BASE\n"); |
| 166 | flash_esel = 2; /* give our best effort to continue */ |
| 167 | } else { |
| 168 | /* invalidate existing TLB entry for flash + promjet */ |
| 169 | disable_tlb(flash_esel); |
| 170 | } |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 171 | |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 172 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 173 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ |
| 174 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ |
| 175 | |
| 176 | return 0; |
| 177 | } |
| 178 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 179 | int board_eth_init(struct bd_info *bis) |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 180 | { |
Bin Meng | 28cedb2 | 2016-01-11 22:41:14 -0800 | [diff] [blame] | 181 | #ifdef CONFIG_TSEC_ENET |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 182 | struct fsl_pq_mdio_info mdio_info; |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 183 | struct tsec_info_struct tsec_info[4]; |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 184 | int num = 0; |
| 185 | |
| 186 | #ifdef CONFIG_TSEC1 |
| 187 | SET_STD_TSEC_INFO(tsec_info[num], 1); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 188 | if (is_serdes_configured(SGMII_TSEC1)) { |
| 189 | puts("eTSEC1 is in sgmii mode.\n"); |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 190 | tsec_info[num].flags |= TSEC_SGMII; |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 191 | } |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 192 | num++; |
| 193 | #endif |
| 194 | #ifdef CONFIG_TSEC2 |
| 195 | SET_STD_TSEC_INFO(tsec_info[num], 2); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 196 | if (is_serdes_configured(SGMII_TSEC2)) { |
| 197 | puts("eTSEC2 is in sgmii mode.\n"); |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 198 | tsec_info[num].flags |= TSEC_SGMII; |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 199 | } |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 200 | num++; |
| 201 | #endif |
| 202 | #ifdef CONFIG_TSEC3 |
| 203 | SET_STD_TSEC_INFO(tsec_info[num], 3); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 204 | if (is_serdes_configured(SGMII_TSEC3)) { |
| 205 | puts("eTSEC3 is in sgmii mode.\n"); |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 206 | tsec_info[num].flags |= TSEC_SGMII; |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 207 | } |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 208 | num++; |
| 209 | #endif |
| 210 | #ifdef CONFIG_TSEC4 |
| 211 | SET_STD_TSEC_INFO(tsec_info[num], 4); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 212 | if (is_serdes_configured(SGMII_TSEC4)) { |
| 213 | puts("eTSEC4 is in sgmii mode.\n"); |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 214 | tsec_info[num].flags |= TSEC_SGMII; |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 215 | } |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 216 | num++; |
| 217 | #endif |
| 218 | |
| 219 | if (!num) { |
| 220 | printf("No TSECs initialized\n"); |
| 221 | |
| 222 | return 0; |
| 223 | } |
| 224 | |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 225 | #ifdef CONFIG_FSL_SGMII_RISER |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 226 | fsl_sgmii_riser_init(tsec_info, num); |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 227 | #endif |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 228 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 229 | mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; |
| 230 | mdio_info.name = DEFAULT_MII_NAME; |
| 231 | fsl_pq_mdio_init(bis, &mdio_info); |
| 232 | |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 233 | tsec_eth_init(bis, tsec_info, num); |
Bin Meng | 28cedb2 | 2016-01-11 22:41:14 -0800 | [diff] [blame] | 234 | #endif |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 235 | |
Kumar Gala | d3b1b66 | 2009-08-08 10:42:30 -0500 | [diff] [blame] | 236 | return pci_eth_init(bis); |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 237 | } |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 238 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 239 | #if defined(CONFIG_OF_BOARD_SETUP) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 240 | int ft_board_setup(void *blob, struct bd_info *bd) |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 241 | { |
Kumar Gala | f281c5c | 2009-02-09 22:03:04 -0600 | [diff] [blame] | 242 | phys_addr_t base; |
| 243 | phys_size_t size; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 244 | |
| 245 | ft_cpu_setup(blob, bd); |
| 246 | |
Simon Glass | da1a134 | 2017-08-03 12:22:15 -0600 | [diff] [blame] | 247 | base = env_get_bootm_low(); |
| 248 | size = env_get_bootm_size(); |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 249 | |
| 250 | fdt_fixup_memory(blob, (u64)base, (u64)size); |
| 251 | |
Kumar Gala | d0f27d3 | 2010-07-08 22:37:44 -0500 | [diff] [blame] | 252 | FT_FSL_PCI_SETUP; |
| 253 | |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 254 | #ifdef CONFIG_FSL_SGMII_RISER |
| 255 | fsl_sgmii_riser_fdt_fixup(blob); |
| 256 | #endif |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 257 | |
| 258 | return 0; |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 259 | } |
| 260 | #endif |