blob: 97e73533ab4b3bcc6cc7157cc3738286578fb233 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05002/*
Kumar Gala365024c2011-01-31 15:51:20 -06003 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05004 */
5
6#include <common.h>
7#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06008#include <env.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060012#include <net.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050013#include <pci.h>
14#include <asm/processor.h>
15#include <asm/mmu.h>
Kumar Galaf81f89f2008-09-22 14:11:11 -050016#include <asm/cache.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050017#include <asm/immap_85xx.h>
Kumar Gala9bbd6432009-04-02 13:22:48 -050018#include <asm/fsl_pci.h>
York Sunf0626592013-09-30 09:22:09 -070019#include <fsl_ddr_sdram.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050020#include <asm/io.h>
Kumar Gala3d020382010-12-15 04:55:20 -060021#include <asm/fsl_serdes.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050022#include <miiphy.h>
Simon Glassdbd79542020-05-10 11:40:11 -060023#include <linux/delay.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090024#include <linux/libfdt.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050025#include <fdt_support.h>
Liu Yuc49bce42008-10-10 11:40:59 +080026#include <tsec.h>
Andy Fleming422effd2011-04-08 02:10:54 -050027#include <fsl_mdio.h>
Kumar Galad3b1b662009-08-08 10:42:30 -050028#include <netdev.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050029
Liu Yuc49bce42008-10-10 11:40:59 +080030#include "../common/sgmii_riser.h"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050031
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050032int checkboard (void)
33{
Kumar Galae21db032009-07-14 22:42:01 -050034 u8 vboot;
35 u8 *pixis_base = (u8 *)PIXIS_BASE;
36
Timur Tabi56953ee2012-03-15 11:42:27 +000037 printf("Board: MPC8572DS Sys ID: 0x%02x, "
Kumar Galae21db032009-07-14 22:42:01 -050038 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
39 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
40 in_8(pixis_base + PIXIS_PVER));
41
42 vboot = in_8(pixis_base + PIXIS_VBOOT);
43 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
44 case PIXIS_VBOOT_LBMAP_NOR0:
45 puts ("vBank: 0\n");
46 break;
47 case PIXIS_VBOOT_LBMAP_PJET:
48 puts ("Promjet\n");
49 break;
50 case PIXIS_VBOOT_LBMAP_NAND:
51 puts ("NAND\n");
52 break;
53 case PIXIS_VBOOT_LBMAP_NOR1:
54 puts ("vBank: 1\n");
55 break;
56 }
57
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050058 return 0;
59}
60
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050061
62#if !defined(CONFIG_SPD_EEPROM)
63/*
64 * Fixed sdram init -- doesn't use serial presence detect.
65 */
66
67phys_size_t fixed_sdram (void)
68{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
York Suna21803d2013-11-18 10:29:32 -080070 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050071 uint d_init;
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
74 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050075
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
77 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
78 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
79 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
80 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
81 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
82 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
83 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
84 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
85 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050086
87#if defined (CONFIG_DDR_ECC)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
89 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
90 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050091#endif
92 asm("sync;isync");
93
94 udelay(500);
95
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050097
98#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
99 d_init = 1;
100 debug("DDR - 1st controller: memory initializing\n");
101 /*
102 * Poll until memory is initialized.
103 * 512 Meg at 400 might hit this 200 times or so.
104 */
105 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
106 udelay(1000);
107 }
108 debug("DDR: memory initialized\n\n");
109 asm("sync; isync");
110 udelay(500);
111#endif
112
113 return 512 * 1024 * 1024;
114}
115
116#endif
117
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500118#ifdef CONFIG_PCI
119void pci_init_board(void)
120{
Kumar Galad165dc52010-12-17 06:53:52 -0600121 struct pci_controller *hose;
Kumar Galafd19d1e2009-09-03 10:20:09 -0500122
Kumar Galad165dc52010-12-17 06:53:52 -0600123 fsl_pcie_init_board(0);
Kumar Galafd19d1e2009-09-03 10:20:09 -0500124
Kumar Galad165dc52010-12-17 06:53:52 -0600125 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500126
Kumar Galad165dc52010-12-17 06:53:52 -0600127 if (hose) {
128 u32 temp32;
129 u8 uli_busno = hose->first_busno + 2;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500130
Kumar Galafd19d1e2009-09-03 10:20:09 -0500131 /*
132 * Activate ULI1575 legacy chip by performing a fake
133 * memory access. Needed to make ULI RTC work.
134 * Device 1d has the first on-board memory BAR.
135 */
Kumar Galad165dc52010-12-17 06:53:52 -0600136 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galafd19d1e2009-09-03 10:20:09 -0500137 PCI_BASE_ADDRESS_1, &temp32);
Kumar Galad165dc52010-12-17 06:53:52 -0600138
Kumar Galafd19d1e2009-09-03 10:20:09 -0500139 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
Kumar Galad165dc52010-12-17 06:53:52 -0600140 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galafd19d1e2009-09-03 10:20:09 -0500141 temp32, 4, 0);
142 debug(" uli1572 read to %p\n", p);
143 in_be32(p);
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500144 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500145 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500146}
147#endif
148
149int board_early_init_r(void)
150{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -0700152 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500153
154 /*
155 * Remap Boot flash + PROMJET region to caching-inhibited
156 * so that flash can be erased properly.
157 */
158
Kumar Galaf81f89f2008-09-22 14:11:11 -0500159 /* Flush d-cache and invalidate i-cache of any FLASH data */
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100160 flush_dcache();
161 invalidate_icache();
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500162
York Sun220c3462014-06-24 21:16:20 -0700163 if (flash_esel == -1) {
164 /* very unlikely unless something is messed up */
165 puts("Error: Could not find TLB for FLASH BASE\n");
166 flash_esel = 2; /* give our best effort to continue */
167 } else {
168 /* invalidate existing TLB entry for flash + promjet */
169 disable_tlb(flash_esel);
170 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500171
Kumar Gala4be8b572008-12-02 14:19:34 -0600172 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500173 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
174 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
175
176 return 0;
177}
178
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900179int board_eth_init(struct bd_info *bis)
Liu Yuc49bce42008-10-10 11:40:59 +0800180{
Bin Meng28cedb22016-01-11 22:41:14 -0800181#ifdef CONFIG_TSEC_ENET
Andy Fleming422effd2011-04-08 02:10:54 -0500182 struct fsl_pq_mdio_info mdio_info;
Liu Yuc49bce42008-10-10 11:40:59 +0800183 struct tsec_info_struct tsec_info[4];
Liu Yuc49bce42008-10-10 11:40:59 +0800184 int num = 0;
185
186#ifdef CONFIG_TSEC1
187 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Galae6dc4842010-12-16 14:28:06 -0600188 if (is_serdes_configured(SGMII_TSEC1)) {
189 puts("eTSEC1 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800190 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600191 }
Liu Yuc49bce42008-10-10 11:40:59 +0800192 num++;
193#endif
194#ifdef CONFIG_TSEC2
195 SET_STD_TSEC_INFO(tsec_info[num], 2);
Kumar Galae6dc4842010-12-16 14:28:06 -0600196 if (is_serdes_configured(SGMII_TSEC2)) {
197 puts("eTSEC2 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800198 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600199 }
Liu Yuc49bce42008-10-10 11:40:59 +0800200 num++;
201#endif
202#ifdef CONFIG_TSEC3
203 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Galae6dc4842010-12-16 14:28:06 -0600204 if (is_serdes_configured(SGMII_TSEC3)) {
205 puts("eTSEC3 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800206 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600207 }
Liu Yuc49bce42008-10-10 11:40:59 +0800208 num++;
209#endif
210#ifdef CONFIG_TSEC4
211 SET_STD_TSEC_INFO(tsec_info[num], 4);
Kumar Galae6dc4842010-12-16 14:28:06 -0600212 if (is_serdes_configured(SGMII_TSEC4)) {
213 puts("eTSEC4 is in sgmii mode.\n");
Liu Yuc49bce42008-10-10 11:40:59 +0800214 tsec_info[num].flags |= TSEC_SGMII;
Kumar Galae6dc4842010-12-16 14:28:06 -0600215 }
Liu Yuc49bce42008-10-10 11:40:59 +0800216 num++;
217#endif
218
219 if (!num) {
220 printf("No TSECs initialized\n");
221
222 return 0;
223 }
224
Andy Flemingacaccae2008-12-05 20:10:22 -0600225#ifdef CONFIG_FSL_SGMII_RISER
Liu Yuc49bce42008-10-10 11:40:59 +0800226 fsl_sgmii_riser_init(tsec_info, num);
Andy Flemingacaccae2008-12-05 20:10:22 -0600227#endif
Liu Yuc49bce42008-10-10 11:40:59 +0800228
Andy Fleming422effd2011-04-08 02:10:54 -0500229 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
230 mdio_info.name = DEFAULT_MII_NAME;
231 fsl_pq_mdio_init(bis, &mdio_info);
232
Liu Yuc49bce42008-10-10 11:40:59 +0800233 tsec_eth_init(bis, tsec_info, num);
Bin Meng28cedb22016-01-11 22:41:14 -0800234#endif
Liu Yuc49bce42008-10-10 11:40:59 +0800235
Kumar Galad3b1b662009-08-08 10:42:30 -0500236 return pci_eth_init(bis);
Liu Yuc49bce42008-10-10 11:40:59 +0800237}
Liu Yuc49bce42008-10-10 11:40:59 +0800238
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500239#if defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900240int ft_board_setup(void *blob, struct bd_info *bd)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500241{
Kumar Galaf281c5c2009-02-09 22:03:04 -0600242 phys_addr_t base;
243 phys_size_t size;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500244
245 ft_cpu_setup(blob, bd);
246
Simon Glassda1a1342017-08-03 12:22:15 -0600247 base = env_get_bootm_low();
248 size = env_get_bootm_size();
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500249
250 fdt_fixup_memory(blob, (u64)base, (u64)size);
251
Kumar Galad0f27d32010-07-08 22:37:44 -0500252 FT_FSL_PCI_SETUP;
253
Andy Flemingacaccae2008-12-05 20:10:22 -0600254#ifdef CONFIG_FSL_SGMII_RISER
255 fsl_sgmii_riser_fdt_fixup(blob);
256#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600257
258 return 0;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500259}
260#endif