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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang35d23df2012-03-26 21:49:05 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChung Liewf6afe722007-06-18 13:50:13 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
TsiChung Liewf6afe722007-06-18 13:50:13 -050010#include <config.h>
TsiChungLiew16723332007-07-05 22:54:42 -050011#include <common.h>
Simon Glass0ffd9db2019-12-28 10:45:06 -070012#include <init.h>
TsiChungLiew16723332007-07-05 22:54:42 -050013#include <asm/immap.h>
Alison Wang35d23df2012-03-26 21:49:05 +000014#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050016
17DECLARE_GLOBAL_DATA_PTR;
18
19int checkboard(void)
20{
21 puts("Board: ");
22 puts("Freescale FireEngine 5329 EVB\n");
23 return 0;
24};
25
Simon Glassd35f3382017-04-06 12:47:05 -060026int dram_init(void)
TsiChung Liewf6afe722007-06-18 13:50:13 -050027{
Alison Wang35d23df2012-03-26 21:49:05 +000028 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liewf6afe722007-06-18 13:50:13 -050029 u32 dramsize, i;
30
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
TsiChung Liewf6afe722007-06-18 13:50:13 -050032
33 for (i = 0x13; i < 0x20; i++) {
34 if (dramsize == (1 << i))
35 break;
36 }
37 i--;
38
Alison Wang35d23df2012-03-26 21:49:05 +000039 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
40 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
41 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050042
43 /* Issue PALL */
Alison Wang35d23df2012-03-26 21:49:05 +000044 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050045
46 /* Issue LEMR */
Alison Wang35d23df2012-03-26 21:49:05 +000047 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
48 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
TsiChung Liewf6afe722007-06-18 13:50:13 -050049
50 udelay(500);
51
52 /* Issue PALL */
Alison Wang35d23df2012-03-26 21:49:05 +000053 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050054
55 /* Perform two refresh cycles */
Alison Wang35d23df2012-03-26 21:49:05 +000056 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
57 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
TsiChung Liewf6afe722007-06-18 13:50:13 -050058
Alison Wang35d23df2012-03-26 21:49:05 +000059 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
TsiChung Liewf6afe722007-06-18 13:50:13 -050060
Alison Wang35d23df2012-03-26 21:49:05 +000061 out_be32(&sdram->ctrl,
62 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChung Liewf6afe722007-06-18 13:50:13 -050063
64 udelay(100);
65
Simon Glass39f90ba2017-03-31 08:40:25 -060066 gd->ram_size = dramsize;
67
68 return 0;
TsiChung Liewf6afe722007-06-18 13:50:13 -050069};
70
71int testdram(void)
72{
73 /* TODO: XXX XXX XXX */
74 printf("DRAM test not implemented!\n");
75
76 return (0);
77}