Blame - configs/chromebook_speedy_defconfig - filogic/uboot

blob: 7891d62af1636eb8e556f662cffde88555a78ecf [file] [log] [blame]

Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	1	CONFIG_ARM=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	2	# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	3	CONFIG_ARCH_ROCKCHIP=y
				4	CONFIG_SYS_TEXT_BASE=0x00100000
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	5	CONFIG_ROCKCHIP_RK3288=y
				6	# CONFIG_SPL_MMC_SUPPORT is not set
				7	CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rini	c9285bf	2019-04-29 15:54:04 -0400	[diff] [blame]	8	CONFIG_NR_DRAM_BANKS=1
				9	CONFIG_SPL_STACK_R_ADDR=0x80000
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	10	CONFIG_DEBUG_UART_BASE=0xff690000
				11	CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	12	CONFIG_SPL_SPI_FLASH_SUPPORT=y
				13	CONFIG_SPL_SPI_SUPPORT=y
				14	CONFIG_DEBUG_UART=y
Simon Glass	4be229d	2019-07-20 20:51:14 -0600	[diff] [blame]	15	CONFIG_USE_PREBOOT=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	16	CONFIG_SILENT_CONSOLE=y
				17	CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
				18	# CONFIG_DISPLAY_CPUINFO is not set
				19	CONFIG_DISPLAY_BOARDINFO_LATE=y
				20	CONFIG_BOARD_EARLY_INIT_F=y
Simon Goldschmidt	cc4078c	2018-09-30 14:31:53 +0200	[diff] [blame]	21	CONFIG_SPL_TEXT_BASE=0xff704000
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	22	# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	23	CONFIG_SPL_STACK_R=y
				24	CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	25	# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
				26	# CONFIG_SPL_CRC32_SUPPORT is not set
				27	CONFIG_SPL_PAYLOAD="u-boot.img"
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	28	CONFIG_SPL_SPI_LOAD=y
				29	CONFIG_CMD_GPIO=y
				30	CONFIG_CMD_GPT=y
				31	CONFIG_CMD_I2C=y
				32	CONFIG_CMD_MMC=y
				33	CONFIG_CMD_SF=y
				34	CONFIG_CMD_SF_TEST=y
				35	CONFIG_CMD_SPI=y
				36	CONFIG_CMD_USB=y
				37	# CONFIG_CMD_SETEXPR is not set
				38	CONFIG_CMD_CACHE=y
				39	CONFIG_CMD_TIME=y
				40	CONFIG_CMD_PMIC=y
				41	CONFIG_CMD_REGULATOR=y
				42	# CONFIG_SPL_DOS_PARTITION is not set
				43	# CONFIG_SPL_EFI_PARTITION is not set
				44	CONFIG_SPL_PARTITION_UUIDS=y
				45	CONFIG_SPL_OF_CONTROL=y
				46	CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
				47	CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
				48	CONFIG_SPL_OF_PLATDATA=y
				49	CONFIG_REGMAP=y
				50	CONFIG_SPL_REGMAP=y
				51	CONFIG_SYSCON=y
				52	CONFIG_SPL_SYSCON=y
				53	# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	54	# CONFIG_SPL_BLK is not set
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	55	CONFIG_CLK=y
				56	CONFIG_SPL_CLK=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	57	CONFIG_ROCKCHIP_GPIO=y
				58	CONFIG_I2C_CROS_EC_TUNNEL=y
				59	CONFIG_SYS_I2C_ROCKCHIP=y
				60	CONFIG_I2C_MUX=y
				61	CONFIG_DM_KEYBOARD=y
				62	CONFIG_CROS_EC_KEYB=y
				63	CONFIG_CROS_EC=y
				64	CONFIG_CROS_EC_SPI=y
				65	CONFIG_PWRSEQ=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	66	# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	67	CONFIG_MMC_DW=y
				68	CONFIG_MMC_DW_ROCKCHIP=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	69	CONFIG_SPI_FLASH=y
				70	CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay	0df8104	2019-02-27 15:20:36 +0100	[diff] [blame]	71	CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko	7a19eec	2019-05-13 13:51:03 +0000	[diff] [blame]	72	CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	73	CONFIG_PINCTRL=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	74	CONFIG_PINCONF=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	75	CONFIG_SPL_PINCTRL=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	76	CONFIG_DM_PMIC=y
				77	# CONFIG_SPL_PMIC_CHILDREN is not set
				78	CONFIG_PMIC_RK8XX=y
				79	CONFIG_DM_REGULATOR_FIXED=y
				80	CONFIG_REGULATOR_RK8XX=y
				81	CONFIG_PWM_ROCKCHIP=y
				82	CONFIG_RAM=y
				83	CONFIG_SPL_RAM=y
				84	CONFIG_DEBUG_UART_SHIFT=2
				85	CONFIG_ROCKCHIP_SERIAL=y
				86	CONFIG_ROCKCHIP_SPI=y
				87	CONFIG_SYSRESET=y
				88	CONFIG_USB=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	89	# CONFIG_SPL_DM_USB is not set
				90	CONFIG_USB_DWC2=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	91	CONFIG_ROCKCHIP_USB2_PHY=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	92	CONFIG_DM_VIDEO=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	93	# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	94	CONFIG_CONSOLE_TRUETYPE=y
				95	CONFIG_DISPLAY=y
				96	CONFIG_VIDEO_ROCKCHIP=y
				97	CONFIG_DISPLAY_ROCKCHIP_EDP=y
				98	CONFIG_DISPLAY_ROCKCHIP_HDMI=y
				99	# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	100	CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer	2708698	2019-01-05 20:12:08 -0600	[diff] [blame]	101	CONFIG_CMD_DHRYSTONE=y
				102	CONFIG_ERRNO_STR=y