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Thomas Reufera27932a2010-11-17 16:08:18 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * (C) Copyright 2008
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
14 * (C) Copyright 2010
15 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
16 *
17 * (C) Copyright 2010-2011
18 * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
19 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020020 * SPDX-License-Identifier: GPL-2.0+
Thomas Reufera27932a2010-11-17 16:08:18 +010021 */
22
23#ifndef __CONFIG_KM8321_COMMON_H
24#define __CONFIG_KM8321_COMMON_H
25
26/*
27 * High Level Configuration Options
28 */
29#define CONFIG_QE /* Has QE */
30#define CONFIG_MPC832x /* MPC832x CPU specific */
31#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
32
Holger Bruncke7bec9b2011-07-04 21:52:52 +000033#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
Thomas Reufera27932a2010-11-17 16:08:18 +010034
35/* include common defines/options for all 83xx Keymile boards */
36#include "km83xx-common.h"
37
Thomas Reufera27932a2010-11-17 16:08:18 +010038/*
39 * System IO Config
40 */
41#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
42
43/*
44 * Hardware Reset Configuration Word
45 */
46#define CONFIG_SYS_HRCW_LOW (\
47 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
48 HRCWL_DDR_TO_SCB_CLK_2X1 | \
49 HRCWL_CSB_TO_CLKIN_2X1 | \
50 HRCWL_CORE_TO_CSB_2_5X1 | \
51 HRCWL_CE_PLL_VCO_DIV_2 | \
52 HRCWL_CE_TO_PLL_1X3)
53
54#define CONFIG_SYS_HRCW_HIGH (\
55 HRCWH_PCI_AGENT | \
56 HRCWH_PCI_ARBITER_DISABLE | \
57 HRCWH_CORE_ENABLE | \
58 HRCWH_FROM_0X00000100 | \
59 HRCWH_BOOTSEQ_DISABLE | \
60 HRCWH_SW_WATCHDOG_DISABLE | \
61 HRCWH_ROM_LOC_LOCAL_16BIT | \
62 HRCWH_BIG_ENDIAN | \
63 HRCWH_LALE_NORMAL)
64
Valentin Longchampb21ae182015-11-17 10:53:31 +010065#define CONFIG_SYS_DDRCDR (\
66 DDRCDR_EN | \
67 DDRCDR_PZ_MAXZ | \
68 DDRCDR_NZ_MAXZ | \
69 DDRCDR_M_ODR)
70
Thomas Reufera27932a2010-11-17 16:08:18 +010071#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
72#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
73 SDRAM_CFG_32_BE | \
Marco Schmid166455f2011-12-14 16:21:42 +010074 SDRAM_CFG_SREN | \
75 SDRAM_CFG_HSE)
Thomas Reufera27932a2010-11-17 16:08:18 +010076
77#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
78#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
79#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
80 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
81
82#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
83 CSCONFIG_ODT_WR_CFG | \
84 CSCONFIG_ROW_BIT_13 | \
85 CSCONFIG_COL_BIT_10)
86
Marco Schmid166455f2011-12-14 16:21:42 +010087#define CONFIG_SYS_DDR_MODE 0x47860242
Thomas Reufera27932a2010-11-17 16:08:18 +010088#define CONFIG_SYS_DDR_MODE2 0x8080c000
89
90#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
91 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
92 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
93 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
94 (0 << TIMING_CFG0_WWT_SHIFT) | \
95 (0 << TIMING_CFG0_RRT_SHIFT) | \
96 (0 << TIMING_CFG0_WRT_SHIFT) | \
97 (0 << TIMING_CFG0_RWT_SHIFT))
98
Marco Schmid166455f2011-12-14 16:21:42 +010099#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
Thomas Reufera27932a2010-11-17 16:08:18 +0100100 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
101 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
Marco Schmid166455f2011-12-14 16:21:42 +0100102 (3 << TIMING_CFG1_WRREC_SHIFT) | \
103 (7 << TIMING_CFG1_REFREC_SHIFT) | \
104 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
105 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
106 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Thomas Reufera27932a2010-11-17 16:08:18 +0100107
108#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
109 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
110 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
111 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
Marco Schmid166455f2011-12-14 16:21:42 +0100112 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
Thomas Reufera27932a2010-11-17 16:08:18 +0100113 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
114 (5 << TIMING_CFG2_CPO_SHIFT))
115
116#define CONFIG_SYS_DDR_TIMING_3 0x00000000
117
Heiko Schocher3a8dd212011-03-08 10:47:39 +0100118#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
Gerlando Falauto1dcad7f2012-10-10 22:13:05 +0000119#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
Thomas Reufera27932a2010-11-17 16:08:18 +0100120
121/* EEprom support */
122#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
123
124/*
125 * Local Bus Configuration & Clock Setup
126 */
Marco Schmid166455f2011-12-14 16:21:42 +0100127#define CONFIG_SYS_LCRR_DBYP 0x80000000
128#define CONFIG_SYS_LCRR_EADC 0x00010000
129#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
130
Thomas Reufera27932a2010-11-17 16:08:18 +0100131#define CONFIG_SYS_LBC_LBCR 0x00000000
132
133/*
134 * MMU Setup
135 */
136#define CONFIG_SYS_IBAT7L (0)
137#define CONFIG_SYS_IBAT7U (0)
138#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
139#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
140
141#endif /* __CONFIG_KM8321_COMMON_H */