Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Freescale Semiconductor |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __LS1043ARDB_H__ |
| 8 | #define __LS1043ARDB_H__ |
| 9 | |
| 10 | #include "ls1043a_common.h" |
| 11 | |
Hou Zhiqiang | f97e602 | 2016-06-28 20:18:17 +0800 | [diff] [blame] | 12 | #if defined(CONFIG_FSL_LS_PPA) |
| 13 | #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT |
| 14 | #define SEC_FIRMWARE_ERET_ADDR_REVERT |
| 15 | #define CONFIG_ARMV8_PSCI |
| 16 | |
Hou Zhiqiang | 7f83a5f | 2016-07-29 19:26:34 +0800 | [diff] [blame] | 17 | #define CONFIG_SYS_LS_PPA_FW_IN_XIP |
| 18 | #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP |
Hou Zhiqiang | f97e602 | 2016-06-28 20:18:17 +0800 | [diff] [blame] | 19 | #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 |
| 20 | #endif |
| 21 | #endif |
| 22 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 23 | #define CONFIG_DISPLAY_CPUINFO |
| 24 | #define CONFIG_DISPLAY_BOARDINFO |
| 25 | |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 26 | #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 27 | #define CONFIG_SYS_TEXT_BASE 0x82000000 |
| 28 | #else |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 29 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 30 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 31 | |
| 32 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 33 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 34 | |
| 35 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
| 36 | #define CONFIG_MISC_INIT_R |
| 37 | |
| 38 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 39 | /* Physical Memory Map */ |
| 40 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
Shaohui Xie | f6c8395 | 2015-11-23 15:23:48 +0800 | [diff] [blame] | 41 | #define CONFIG_NR_DRAM_BANKS 2 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 42 | |
| 43 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 44 | |
| 45 | #define CONFIG_FSL_DDR_BIST |
| 46 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
| 47 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 48 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 49 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 50 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 51 | #ifdef CONFIG_RAMBOOT_PBL |
| 52 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg |
| 53 | #endif |
| 54 | |
| 55 | #ifdef CONFIG_NAND_BOOT |
| 56 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |
| 57 | #endif |
| 58 | |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 59 | #ifdef CONFIG_SD_BOOT |
| 60 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |
| 61 | #endif |
| 62 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 63 | /* |
| 64 | * NOR Flash Definitions |
| 65 | */ |
| 66 | #define CONFIG_SYS_NOR_CSPR_EXT (0x0) |
| 67 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 68 | #define CONFIG_SYS_NOR_CSPR \ |
| 69 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 70 | CSPR_PORT_SIZE_16 | \ |
| 71 | CSPR_MSEL_NOR | \ |
| 72 | CSPR_V) |
| 73 | |
| 74 | /* NOR Flash Timing Params */ |
| 75 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 76 | CSOR_NOR_TRHZ_80) |
| 77 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
| 78 | FTIM0_NOR_TEADC(0x1) | \ |
| 79 | FTIM0_NOR_TAVDS(0x0) | \ |
| 80 | FTIM0_NOR_TEAHC(0xc)) |
| 81 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ |
| 82 | FTIM1_NOR_TRAD_NOR(0xb) | \ |
| 83 | FTIM1_NOR_TSEQRAD_NOR(0x9)) |
| 84 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ |
| 85 | FTIM2_NOR_TCH(0x4) | \ |
| 86 | FTIM2_NOR_TWPH(0x8) | \ |
| 87 | FTIM2_NOR_TWP(0x10)) |
| 88 | #define CONFIG_SYS_NOR_FTIM3 0 |
| 89 | #define CONFIG_SYS_IFC_CCR 0x01000000 |
| 90 | |
| 91 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 92 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 93 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 94 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 95 | |
| 96 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 97 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
| 98 | |
| 99 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 100 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 101 | |
| 102 | /* |
| 103 | * NAND Flash Definitions |
| 104 | */ |
| 105 | #define CONFIG_NAND_FSL_IFC |
| 106 | |
| 107 | #define CONFIG_SYS_NAND_BASE 0x7e800000 |
| 108 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 109 | |
| 110 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 111 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 112 | | CSPR_PORT_SIZE_8 \ |
| 113 | | CSPR_MSEL_NAND \ |
| 114 | | CSPR_V) |
| 115 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 116 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 117 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 118 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 119 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 120 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 121 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ |
| 122 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 123 | |
| 124 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 125 | |
| 126 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
| 127 | FTIM0_NAND_TWP(0x18) | \ |
| 128 | FTIM0_NAND_TWCHT(0x7) | \ |
| 129 | FTIM0_NAND_TWH(0xa)) |
| 130 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 131 | FTIM1_NAND_TWBE(0x39) | \ |
| 132 | FTIM1_NAND_TRR(0xe) | \ |
| 133 | FTIM1_NAND_TRP(0x18)) |
| 134 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
| 135 | FTIM2_NAND_TREH(0xa) | \ |
| 136 | FTIM2_NAND_TWHRE(0x1e)) |
| 137 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 138 | |
| 139 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 140 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 141 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 142 | #define CONFIG_CMD_NAND |
| 143 | |
| 144 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 145 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 146 | #ifdef CONFIG_NAND_BOOT |
| 147 | #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ |
| 148 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
| 149 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) |
| 150 | #endif |
| 151 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 152 | /* |
| 153 | * CPLD |
| 154 | */ |
| 155 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| 156 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 157 | |
| 158 | #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) |
| 159 | #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| 160 | CSPR_PORT_SIZE_8 | \ |
| 161 | CSPR_MSEL_GPCM | \ |
| 162 | CSPR_V) |
| 163 | #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| 164 | #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 165 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 166 | CSOR_NOR_TRHZ_80) |
| 167 | |
| 168 | /* CPLD Timing parameters for IFC GPCM */ |
| 169 | #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
| 170 | FTIM0_GPCM_TEADC(0xf) | \ |
| 171 | FTIM0_GPCM_TEAHC(0xf)) |
| 172 | #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 173 | FTIM1_GPCM_TRAD(0x3f)) |
| 174 | #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 175 | FTIM2_GPCM_TCH(0xf) | \ |
| 176 | FTIM2_GPCM_TWP(0xff)) |
| 177 | #define CONFIG_SYS_CPLD_FTIM3 0x0 |
| 178 | |
| 179 | /* IFC Timing Params */ |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 180 | #ifdef CONFIG_NAND_BOOT |
| 181 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 182 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 183 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 184 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 185 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 186 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 187 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 188 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 189 | |
| 190 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 191 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| 192 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 193 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 194 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 195 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 196 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 197 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 198 | #else |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 199 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 200 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 201 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 202 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 203 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 204 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 205 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 206 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 207 | |
| 208 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 209 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 210 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 211 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 212 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 213 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 214 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 215 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 216 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 217 | |
| 218 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT |
| 219 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR |
| 220 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK |
| 221 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR |
| 222 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 |
| 223 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 |
| 224 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 |
| 225 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 |
| 226 | |
| 227 | /* EEPROM */ |
| 228 | #define CONFIG_ID_EEPROM |
| 229 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 230 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 231 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
| 232 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 233 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 234 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 235 | |
| 236 | /* |
| 237 | * Environment |
| 238 | */ |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 239 | #define CONFIG_ENV_OVERWRITE |
| 240 | |
| 241 | #if defined(CONFIG_NAND_BOOT) |
| 242 | #define CONFIG_ENV_IS_IN_NAND |
| 243 | #define CONFIG_ENV_SIZE 0x2000 |
| 244 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 245 | #elif defined(CONFIG_SD_BOOT) |
| 246 | #define CONFIG_ENV_OFFSET (1024 * 1024) |
| 247 | #define CONFIG_ENV_IS_IN_MMC |
| 248 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 249 | #define CONFIG_ENV_SIZE 0x2000 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 250 | #else |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 251 | #define CONFIG_ENV_IS_IN_FLASH |
| 252 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) |
| 253 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 254 | #define CONFIG_ENV_SIZE 0x20000 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 255 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 256 | |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 257 | /* FMan */ |
| 258 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 259 | #define CONFIG_FMAN_ENET |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 260 | #define CONFIG_PHYLIB |
| 261 | #define CONFIG_PHYLIB_10G |
| 262 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| 263 | |
| 264 | #define CONFIG_PHY_VITESSE |
| 265 | #define CONFIG_PHY_REALTEK |
| 266 | #define CONFIG_PHY_AQUANTIA |
Shaohui Xie | 9f4d011 | 2016-04-29 22:07:21 +0800 | [diff] [blame] | 267 | #define AQR105_IRQ_MASK 0x40000000 |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 268 | |
| 269 | #define RGMII_PHY1_ADDR 0x1 |
| 270 | #define RGMII_PHY2_ADDR 0x2 |
| 271 | |
| 272 | #define QSGMII_PORT1_PHY_ADDR 0x4 |
| 273 | #define QSGMII_PORT2_PHY_ADDR 0x5 |
| 274 | #define QSGMII_PORT3_PHY_ADDR 0x6 |
| 275 | #define QSGMII_PORT4_PHY_ADDR 0x7 |
| 276 | |
| 277 | #define FM1_10GEC1_PHY_ADDR 0x1 |
| 278 | |
| 279 | #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| 280 | #endif |
| 281 | |
Zhao Qiang | 0be9be8 | 2016-02-05 10:04:17 +0800 | [diff] [blame] | 282 | /* QE */ |
| 283 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| 284 | !defined(CONFIG_QSPI_BOOT) |
| 285 | #define CONFIG_U_QE |
| 286 | #endif |
| 287 | #define CONFIG_SYS_QE_FW_ADDR 0x60600000 |
| 288 | |
Gong Qianyu | 0ea9b3d | 2015-11-11 17:58:40 +0800 | [diff] [blame] | 289 | /* USB */ |
| 290 | #define CONFIG_HAS_FSL_XHCI_USB |
| 291 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
Gong Qianyu | 0ea9b3d | 2015-11-11 17:58:40 +0800 | [diff] [blame] | 292 | #define CONFIG_USB_XHCI_FSL |
Gong Qianyu | 0ea9b3d | 2015-11-11 17:58:40 +0800 | [diff] [blame] | 293 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
| 294 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
Gong Qianyu | 0ea9b3d | 2015-11-11 17:58:40 +0800 | [diff] [blame] | 295 | #endif |
| 296 | |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 297 | /* SATA */ |
| 298 | #define CONFIG_LIBATA |
| 299 | #define CONFIG_SCSI_AHCI |
| 300 | #define CONFIG_CMD_SCSI |
| 301 | #ifndef CONFIG_CMD_FAT |
| 302 | #define CONFIG_CMD_FAT |
| 303 | #endif |
| 304 | #ifndef CONFIG_CMD_EXT2 |
| 305 | #define CONFIG_CMD_EXT2 |
| 306 | #endif |
| 307 | #define CONFIG_DOS_PARTITION |
| 308 | #define CONFIG_BOARD_LATE_INIT |
| 309 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
| 310 | #define CONFIG_SYS_SCSI_MAX_LUN 2 |
| 311 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 312 | CONFIG_SYS_SCSI_MAX_LUN) |
| 313 | #define SCSI_VEND_ID 0x1b4b |
| 314 | #define SCSI_DEV_ID 0x9170 |
| 315 | #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} |
| 316 | #define CONFIG_PCI |
| 317 | |
Aneesh Bansal | b3e9820 | 2015-12-08 13:54:29 +0530 | [diff] [blame] | 318 | #include <asm/fsl_secure_boot.h> |
| 319 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 320 | #endif /* __LS1043ARDB_H__ */ |