blob: 070aadfa2063a7ee9c40238085f145e87b7b73b4 [file] [log] [blame]
Ted Chen9b6dbd42016-01-20 14:24:52 +08001/*
2 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 *
Stefan Roese47c50972016-06-29 07:58:05 +02006 */
Ted Chen9b6dbd42016-01-20 14:24:52 +08007
8#include <common.h>
Stefan Roese47c50972016-06-29 07:58:05 +02009#include <dm.h>
Ted Chen9b6dbd42016-01-20 14:24:52 +080010#include <errno.h>
11#include <malloc.h>
12#include <usb.h>
13#include <usb/lin_gadget_compat.h>
14#include <linux/mii.h>
15#include <linux/bitops.h>
16#include "usb_ether.h"
17#include "r8152.h"
18
Stefan Roese47c50972016-06-29 07:58:05 +020019#ifndef CONFIG_DM_ETH
Ted Chen9b6dbd42016-01-20 14:24:52 +080020/* local vars */
21static int curr_eth_dev; /* index for name of next device detected */
22
23struct r8152_dongle {
24 unsigned short vendor;
25 unsigned short product;
26};
27
Ted Chen9b6dbd42016-01-20 14:24:52 +080028static const struct r8152_dongle const r8152_dongles[] = {
29 /* Realtek */
30 { 0x0bda, 0x8050 },
31 { 0x0bda, 0x8152 },
32 { 0x0bda, 0x8153 },
33
34 /* Samsung */
35 { 0x04e8, 0xa101 },
36
37 /* Lenovo */
38 { 0x17ef, 0x304f },
39 { 0x17ef, 0x3052 },
40 { 0x17ef, 0x3054 },
41 { 0x17ef, 0x3057 },
42 { 0x17ef, 0x7205 },
43 { 0x17ef, 0x720a },
44 { 0x17ef, 0x720b },
45 { 0x17ef, 0x720c },
46
47 /* TP-LINK */
48 { 0x2357, 0x0601 },
49
50 /* Nvidia */
51 { 0x0955, 0x09ff },
52};
Stefan Roese47c50972016-06-29 07:58:05 +020053#endif
54
55struct r8152_version {
56 unsigned short tcr;
57 unsigned short version;
58 bool gmii;
59};
Ted Chen9b6dbd42016-01-20 14:24:52 +080060
61static const struct r8152_version const r8152_versions[] = {
62 { 0x4c00, RTL_VER_01, 0 },
63 { 0x4c10, RTL_VER_02, 0 },
64 { 0x5c00, RTL_VER_03, 1 },
65 { 0x5c10, RTL_VER_04, 1 },
66 { 0x5c20, RTL_VER_05, 1 },
67 { 0x5c30, RTL_VER_06, 1 },
68 { 0x4800, RTL_VER_07, 0 },
69};
70
71static
72int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
73{
74 return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
75 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
76 value, index, data, size, 500);
77}
78
79static
80int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
81{
82 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
83 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
84 value, index, data, size, 500);
85}
86
87int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
88 void *data, u16 type)
89{
90 u16 burst_size = 64;
91 int ret;
92 int txsize;
93
94 /* both size and index must be 4 bytes align */
95 if ((size & 3) || !size || (index & 3) || !data)
96 return -EINVAL;
97
98 if (index + size > 0xffff)
99 return -EINVAL;
100
101 while (size) {
102 txsize = min(size, burst_size);
103 ret = get_registers(tp, index, type, txsize, data);
104 if (ret < 0)
105 break;
106
107 index += txsize;
108 data += txsize;
109 size -= txsize;
110 }
111
112 return ret;
113}
114
115int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
116 u16 size, void *data, u16 type)
117{
118 int ret;
119 u16 byteen_start, byteen_end, byte_en_to_hw;
120 u16 burst_size = 512;
121 int txsize;
122
123 /* both size and index must be 4 bytes align */
124 if ((size & 3) || !size || (index & 3) || !data)
125 return -EINVAL;
126
127 if (index + size > 0xffff)
128 return -EINVAL;
129
130 byteen_start = byteen & BYTE_EN_START_MASK;
131 byteen_end = byteen & BYTE_EN_END_MASK;
132
133 byte_en_to_hw = byteen_start | (byteen_start << 4);
134 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
135 if (ret < 0)
136 return ret;
137
138 index += 4;
139 data += 4;
140 size -= 4;
141
142 if (size) {
143 size -= 4;
144
145 while (size) {
146 txsize = min(size, burst_size);
147
148 ret = set_registers(tp, index,
149 type | BYTE_EN_DWORD,
150 txsize, data);
151 if (ret < 0)
152 return ret;
153
154 index += txsize;
155 data += txsize;
156 size -= txsize;
157 }
158
159 byte_en_to_hw = byteen_end | (byteen_end >> 4);
160 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
161 if (ret < 0)
162 return ret;
163 }
164
165 return ret;
166}
167
168int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
169{
170 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
171}
172
173int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
174{
175 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
176}
177
178int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
179{
180 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
181}
182
183int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
184{
185 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
186}
187
188u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
189{
190 __le32 data;
191
192 generic_ocp_read(tp, index, sizeof(data), &data, type);
193
194 return __le32_to_cpu(data);
195}
196
197void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
198{
199 __le32 tmp = __cpu_to_le32(data);
200
201 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
202}
203
204u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
205{
206 u32 data;
207 __le32 tmp;
208 u8 shift = index & 2;
209
210 index &= ~3;
211
212 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
213
214 data = __le32_to_cpu(tmp);
215 data >>= (shift * 8);
216 data &= 0xffff;
217
218 return data;
219}
220
221void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
222{
223 u32 mask = 0xffff;
224 __le32 tmp;
225 u16 byen = BYTE_EN_WORD;
226 u8 shift = index & 2;
227
228 data &= mask;
229
230 if (index & 2) {
231 byen <<= shift;
232 mask <<= (shift * 8);
233 data <<= (shift * 8);
234 index &= ~3;
235 }
236
237 tmp = __cpu_to_le32(data);
238
239 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
240}
241
242u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
243{
244 u32 data;
245 __le32 tmp;
246 u8 shift = index & 3;
247
248 index &= ~3;
249
250 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
251
252 data = __le32_to_cpu(tmp);
253 data >>= (shift * 8);
254 data &= 0xff;
255
256 return data;
257}
258
259void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
260{
261 u32 mask = 0xff;
262 __le32 tmp;
263 u16 byen = BYTE_EN_BYTE;
264 u8 shift = index & 3;
265
266 data &= mask;
267
268 if (index & 3) {
269 byen <<= shift;
270 mask <<= (shift * 8);
271 data <<= (shift * 8);
272 index &= ~3;
273 }
274
275 tmp = __cpu_to_le32(data);
276
277 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
278}
279
280u16 ocp_reg_read(struct r8152 *tp, u16 addr)
281{
282 u16 ocp_base, ocp_index;
283
284 ocp_base = addr & 0xf000;
285 if (ocp_base != tp->ocp_base) {
286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
287 tp->ocp_base = ocp_base;
288 }
289
290 ocp_index = (addr & 0x0fff) | 0xb000;
291 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
292}
293
294void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
295{
296 u16 ocp_base, ocp_index;
297
298 ocp_base = addr & 0xf000;
299 if (ocp_base != tp->ocp_base) {
300 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
301 tp->ocp_base = ocp_base;
302 }
303
304 ocp_index = (addr & 0x0fff) | 0xb000;
305 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
306}
307
308static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
309{
310 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
311}
312
313static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
314{
315 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
316}
317
318void sram_write(struct r8152 *tp, u16 addr, u16 data)
319{
320 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
321 ocp_reg_write(tp, OCP_SRAM_DATA, data);
322}
323
324int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
325 const u32 mask, bool set, unsigned int timeout)
326{
327 u32 val;
328
329 while (--timeout) {
330 if (ocp_reg)
331 val = ocp_reg_read(tp, index);
332 else
333 val = ocp_read_dword(tp, type, index);
334
335 if (!set)
336 val = ~val;
337
338 if ((val & mask) == mask)
339 return 0;
340
341 mdelay(1);
342 }
343
344 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
345 __func__, index, mask, timeout);
346
347 return -ETIMEDOUT;
348}
349
350static void r8152b_reset_packet_filter(struct r8152 *tp)
351{
352 u32 ocp_data;
353
354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
355 ocp_data &= ~FMC_FCR_MCU_EN;
356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
357 ocp_data |= FMC_FCR_MCU_EN;
358 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
359}
360
361static void rtl8152_wait_fifo_empty(struct r8152 *tp)
362{
363 int ret;
364
365 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
366 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
367 if (ret)
368 debug("Timeout waiting for FIFO empty\n");
369
370 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
371 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
372 if (ret)
373 debug("Timeout waiting for TX empty\n");
374}
375
376static void rtl8152_nic_reset(struct r8152 *tp)
377{
378 int ret;
379 u32 ocp_data;
380
381 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
382 ocp_data |= BIST_CTRL_SW_RESET;
383 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
384
385 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
386 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
387 if (ret)
388 debug("Timeout waiting for NIC reset\n");
389}
390
391static u8 rtl8152_get_speed(struct r8152 *tp)
392{
393 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
394}
395
396static void rtl_set_eee_plus(struct r8152 *tp)
397{
398 u32 ocp_data;
399
400 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
401 ocp_data &= ~EEEP_CR_EEEP_TX;
402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
403}
404
405static void rxdy_gated_en(struct r8152 *tp, bool enable)
406{
407 u32 ocp_data;
408
409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
410 if (enable)
411 ocp_data |= RXDY_GATED_EN;
412 else
413 ocp_data &= ~RXDY_GATED_EN;
414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
415}
416
417static void rtl8152_set_rx_mode(struct r8152 *tp)
418{
419 u32 ocp_data;
420 __le32 tmp[2];
421
422 tmp[0] = 0xffffffff;
423 tmp[1] = 0xffffffff;
424
425 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
426
427 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
428 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
429 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
430}
431
432static int rtl_enable(struct r8152 *tp)
433{
434 u32 ocp_data;
435
436 r8152b_reset_packet_filter(tp);
437
438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
439 ocp_data |= PLA_CR_RE | PLA_CR_TE;
440 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
441
442 rxdy_gated_en(tp, false);
443
444 rtl8152_set_rx_mode(tp);
445
446 return 0;
447}
448
449static int rtl8152_enable(struct r8152 *tp)
450{
451 rtl_set_eee_plus(tp);
452
453 return rtl_enable(tp);
454}
455
456static void r8153_set_rx_early_timeout(struct r8152 *tp)
457{
458 u32 ocp_data = tp->coalesce / 8;
459
460 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
461}
462
463static void r8153_set_rx_early_size(struct r8152 *tp)
464{
465 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
466
467 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
468}
469
470static int rtl8153_enable(struct r8152 *tp)
471{
472 rtl_set_eee_plus(tp);
473 r8153_set_rx_early_timeout(tp);
474 r8153_set_rx_early_size(tp);
475
476 return rtl_enable(tp);
477}
478
479static void rtl_disable(struct r8152 *tp)
480{
481 u32 ocp_data;
482
483 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
484 ocp_data &= ~RCR_ACPT_ALL;
485 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
486
487 rxdy_gated_en(tp, true);
488
489 rtl8152_wait_fifo_empty(tp);
490 rtl8152_nic_reset(tp);
491}
492
493static void r8152_power_cut_en(struct r8152 *tp, bool enable)
494{
495 u32 ocp_data;
496
497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
498 if (enable)
499 ocp_data |= POWER_CUT;
500 else
501 ocp_data &= ~POWER_CUT;
502 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
503
504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
505 ocp_data &= ~RESUME_INDICATE;
506 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
507}
508
509static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
510{
511 u32 ocp_data;
512
513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
514 if (enable)
515 ocp_data |= CPCR_RX_VLAN;
516 else
517 ocp_data &= ~CPCR_RX_VLAN;
518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
519}
520
521static void r8153_u1u2en(struct r8152 *tp, bool enable)
522{
523 u8 u1u2[8];
524
525 if (enable)
526 memset(u1u2, 0xff, sizeof(u1u2));
527 else
528 memset(u1u2, 0x00, sizeof(u1u2));
529
530 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
531}
532
533static void r8153_u2p3en(struct r8152 *tp, bool enable)
534{
535 u32 ocp_data;
536
537 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
538 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
539 ocp_data |= U2P3_ENABLE;
540 else
541 ocp_data &= ~U2P3_ENABLE;
542 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
543}
544
545static void r8153_power_cut_en(struct r8152 *tp, bool enable)
546{
547 u32 ocp_data;
548
549 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
550 if (enable)
551 ocp_data |= PWR_EN | PHASE2_EN;
552 else
553 ocp_data &= ~(PWR_EN | PHASE2_EN);
554 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
555
556 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
557 ocp_data &= ~PCUT_STATUS;
558 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
559}
560
561static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
562{
563 int ret;
564 unsigned char enetaddr[8] = {0};
565
566 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
567 if (ret < 0)
568 return ret;
569
570 memcpy(macaddr, enetaddr, ETH_ALEN);
571 return 0;
572}
573
574static void r8152b_disable_aldps(struct r8152 *tp)
575{
576 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
577 mdelay(20);
578}
579
580static void r8152b_enable_aldps(struct r8152 *tp)
581{
582 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
583 LINKENA | DIS_SDSAVE);
584}
585
586static void rtl8152_disable(struct r8152 *tp)
587{
588 r8152b_disable_aldps(tp);
589 rtl_disable(tp);
590 r8152b_enable_aldps(tp);
591}
592
593static void r8152b_hw_phy_cfg(struct r8152 *tp)
594{
595 u16 data;
596
597 data = r8152_mdio_read(tp, MII_BMCR);
598 if (data & BMCR_PDOWN) {
599 data &= ~BMCR_PDOWN;
600 r8152_mdio_write(tp, MII_BMCR, data);
601 }
602
603 r8152b_firmware(tp);
604}
605
606static void rtl8152_reinit_ll(struct r8152 *tp)
607{
608 u32 ocp_data;
609 int ret;
610
611 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
612 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
613 if (ret)
614 debug("Timeout waiting for link list ready\n");
615
616 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
617 ocp_data |= RE_INIT_LL;
618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
619
620 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
621 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
622 if (ret)
623 debug("Timeout waiting for link list ready\n");
624}
625
626static void r8152b_exit_oob(struct r8152 *tp)
627{
628 u32 ocp_data;
629
630 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
631 ocp_data &= ~RCR_ACPT_ALL;
632 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
633
634 rxdy_gated_en(tp, true);
635 r8152b_hw_phy_cfg(tp);
636
637 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
638 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
639
640 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
641 ocp_data &= ~NOW_IS_OOB;
642 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
643
644 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
645 ocp_data &= ~MCU_BORW_EN;
646 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
647
648 rtl8152_reinit_ll(tp);
649 rtl8152_nic_reset(tp);
650
651 /* rx share fifo credit full threshold */
652 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
653
654 if (tp->udev->speed == USB_SPEED_FULL ||
655 tp->udev->speed == USB_SPEED_LOW) {
656 /* rx share fifo credit near full threshold */
657 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
658 RXFIFO_THR2_FULL);
659 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
660 RXFIFO_THR3_FULL);
661 } else {
662 /* rx share fifo credit near full threshold */
663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
664 RXFIFO_THR2_HIGH);
665 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
666 RXFIFO_THR3_HIGH);
667 }
668
669 /* TX share fifo free credit full threshold */
670 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
671
672 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
673 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
674 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
675 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
676
677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
678
679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
680 ocp_data |= TCR0_AUTO_FIFO;
681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
682}
683
684static void r8152b_enter_oob(struct r8152 *tp)
685{
686 u32 ocp_data;
687
688 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
689 ocp_data &= ~NOW_IS_OOB;
690 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
691
692 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
693 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
694 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
695
696 rtl_disable(tp);
697
698 rtl8152_reinit_ll(tp);
699
700 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
701
702 rtl_rx_vlan_en(tp, false);
703
704 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
705 ocp_data |= ALDPS_PROXY_MODE;
706 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
707
708 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
709 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
710 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
711
712 rxdy_gated_en(tp, false);
713
714 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
715 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
716 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
717}
718
719static void r8153_hw_phy_cfg(struct r8152 *tp)
720{
721 u32 ocp_data;
722 u16 data;
723
724 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
725 tp->version == RTL_VER_05)
726 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
727
728 data = r8152_mdio_read(tp, MII_BMCR);
729 if (data & BMCR_PDOWN) {
730 data &= ~BMCR_PDOWN;
731 r8152_mdio_write(tp, MII_BMCR, data);
732 }
733
734 r8153_firmware(tp);
735
736 if (tp->version == RTL_VER_03) {
737 data = ocp_reg_read(tp, OCP_EEE_CFG);
738 data &= ~CTAP_SHORT_EN;
739 ocp_reg_write(tp, OCP_EEE_CFG, data);
740 }
741
742 data = ocp_reg_read(tp, OCP_POWER_CFG);
743 data |= EEE_CLKDIV_EN;
744 ocp_reg_write(tp, OCP_POWER_CFG, data);
745
746 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
747 data |= EN_10M_BGOFF;
748 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
749 data = ocp_reg_read(tp, OCP_POWER_CFG);
750 data |= EN_10M_PLLOFF;
751 ocp_reg_write(tp, OCP_POWER_CFG, data);
752 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
753
754 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
755 ocp_data |= PFM_PWM_SWITCH;
756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
757
758 /* Enable LPF corner auto tune */
759 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
760
761 /* Adjust 10M Amplitude */
762 sram_write(tp, SRAM_10M_AMP1, 0x00af);
763 sram_write(tp, SRAM_10M_AMP2, 0x0208);
764}
765
766static void r8153_first_init(struct r8152 *tp)
767{
768 u32 ocp_data;
769
770 rxdy_gated_en(tp, true);
771
772 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
773 ocp_data &= ~RCR_ACPT_ALL;
774 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
775
776 r8153_hw_phy_cfg(tp);
777
778 rtl8152_nic_reset(tp);
779
780 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
781 ocp_data &= ~NOW_IS_OOB;
782 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
783
784 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
785 ocp_data &= ~MCU_BORW_EN;
786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
787
788 rtl8152_reinit_ll(tp);
789
790 rtl_rx_vlan_en(tp, false);
791
792 ocp_data = RTL8153_RMS;
793 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
794 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
795
796 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
797 ocp_data |= TCR0_AUTO_FIFO;
798 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
799
800 rtl8152_nic_reset(tp);
801
802 /* rx share fifo credit full threshold */
803 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
806 /* TX share fifo free credit full threshold */
807 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
808
809 /* rx aggregation */
810 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
811
812 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
813 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
814}
815
816static void r8153_enter_oob(struct r8152 *tp)
817{
818 u32 ocp_data;
819
820 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
821 ocp_data &= ~NOW_IS_OOB;
822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
823
824 rtl_disable(tp);
825
826 rtl8152_reinit_ll(tp);
827
828 ocp_data = RTL8153_RMS;
829 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
830
831 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
832 ocp_data &= ~TEREDO_WAKE_MASK;
833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
834
835 rtl_rx_vlan_en(tp, false);
836
837 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
838 ocp_data |= ALDPS_PROXY_MODE;
839 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
840
841 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
842 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
843 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
844
845 rxdy_gated_en(tp, false);
846
847 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
848 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
849 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
850}
851
852static void r8153_disable_aldps(struct r8152 *tp)
853{
854 u16 data;
855
856 data = ocp_reg_read(tp, OCP_POWER_CFG);
857 data &= ~EN_ALDPS;
858 ocp_reg_write(tp, OCP_POWER_CFG, data);
859 mdelay(20);
860}
861
862static void rtl8153_disable(struct r8152 *tp)
863{
864 r8153_disable_aldps(tp);
865 rtl_disable(tp);
866}
867
868static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
869{
870 u16 bmcr, anar, gbcr;
871
872 anar = r8152_mdio_read(tp, MII_ADVERTISE);
873 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
874 ADVERTISE_100HALF | ADVERTISE_100FULL);
875 if (tp->supports_gmii) {
876 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
877 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
878 } else {
879 gbcr = 0;
880 }
881
882 if (autoneg == AUTONEG_DISABLE) {
883 if (speed == SPEED_10) {
884 bmcr = 0;
885 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
886 } else if (speed == SPEED_100) {
887 bmcr = BMCR_SPEED100;
888 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
889 } else if (speed == SPEED_1000 && tp->supports_gmii) {
890 bmcr = BMCR_SPEED1000;
891 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
892 } else {
893 return -EINVAL;
894 }
895
896 if (duplex == DUPLEX_FULL)
897 bmcr |= BMCR_FULLDPLX;
898 } else {
899 if (speed == SPEED_10) {
900 if (duplex == DUPLEX_FULL)
901 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
902 else
903 anar |= ADVERTISE_10HALF;
904 } else if (speed == SPEED_100) {
905 if (duplex == DUPLEX_FULL) {
906 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
907 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
908 } else {
909 anar |= ADVERTISE_10HALF;
910 anar |= ADVERTISE_100HALF;
911 }
912 } else if (speed == SPEED_1000 && tp->supports_gmii) {
913 if (duplex == DUPLEX_FULL) {
914 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
915 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
916 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
917 } else {
918 anar |= ADVERTISE_10HALF;
919 anar |= ADVERTISE_100HALF;
920 gbcr |= ADVERTISE_1000HALF;
921 }
922 } else {
923 return -EINVAL;
924 }
925
926 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
927 }
928
929 if (tp->supports_gmii)
930 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
931
932 r8152_mdio_write(tp, MII_ADVERTISE, anar);
933 r8152_mdio_write(tp, MII_BMCR, bmcr);
934
935 return 0;
936}
937
938static void rtl8152_up(struct r8152 *tp)
939{
940 r8152b_disable_aldps(tp);
941 r8152b_exit_oob(tp);
942 r8152b_enable_aldps(tp);
943}
944
945static void rtl8152_down(struct r8152 *tp)
946{
947 r8152_power_cut_en(tp, false);
948 r8152b_disable_aldps(tp);
949 r8152b_enter_oob(tp);
950 r8152b_enable_aldps(tp);
951}
952
953static void rtl8153_up(struct r8152 *tp)
954{
955 r8153_u1u2en(tp, false);
956 r8153_disable_aldps(tp);
957 r8153_first_init(tp);
958 r8153_u2p3en(tp, false);
959}
960
961static void rtl8153_down(struct r8152 *tp)
962{
963 r8153_u1u2en(tp, false);
964 r8153_u2p3en(tp, false);
965 r8153_power_cut_en(tp, false);
966 r8153_disable_aldps(tp);
967 r8153_enter_oob(tp);
968}
969
970static void r8152b_get_version(struct r8152 *tp)
971{
972 u32 ocp_data;
973 u16 tcr;
974 int i;
975
976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
977 tcr = (u16)(ocp_data & VERSION_MASK);
978
979 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
980 if (tcr == r8152_versions[i].tcr) {
981 /* Found a supported version */
982 tp->version = r8152_versions[i].version;
983 tp->supports_gmii = r8152_versions[i].gmii;
984 break;
985 }
986 }
987
988 if (tp->version == RTL_VER_UNKNOWN)
989 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
990}
991
992static void r8152b_enable_fc(struct r8152 *tp)
993{
994 u16 anar;
995 anar = r8152_mdio_read(tp, MII_ADVERTISE);
996 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
997 r8152_mdio_write(tp, MII_ADVERTISE, anar);
998}
999
1000static void rtl_tally_reset(struct r8152 *tp)
1001{
1002 u32 ocp_data;
1003
1004 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1005 ocp_data |= TALLY_RESET;
1006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1007}
1008
1009static void r8152b_init(struct r8152 *tp)
1010{
1011 u32 ocp_data;
1012
1013 r8152b_disable_aldps(tp);
1014
1015 if (tp->version == RTL_VER_01) {
1016 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1017 ocp_data &= ~LED_MODE_MASK;
1018 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1019 }
1020
1021 r8152_power_cut_en(tp, false);
1022
1023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1024 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1027 ocp_data &= ~MCU_CLK_RATIO_MASK;
1028 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1029 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1030 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1031 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1033
1034 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1035 ocp_data |= BIT(15);
1036 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1037 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1038 ocp_data &= ~BIT(15);
1039 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1040
1041 r8152b_enable_fc(tp);
1042 rtl_tally_reset(tp);
1043
1044 /* enable rx aggregation */
1045 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1046
1047 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1048 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1049}
1050
1051static void r8153_init(struct r8152 *tp)
1052{
1053 int i;
1054 u32 ocp_data;
1055
1056 r8153_disable_aldps(tp);
1057 r8153_u1u2en(tp, false);
1058
1059 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1060 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1061
1062 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1063 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1064 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1065 break;
1066
1067 mdelay(1);
1068 }
1069
1070 r8153_u2p3en(tp, false);
1071
1072 if (tp->version == RTL_VER_04) {
1073 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1074 ocp_data &= ~pwd_dn_scale_mask;
1075 ocp_data |= pwd_dn_scale(96);
1076 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1077
1078 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1079 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1080 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1081 } else if (tp->version == RTL_VER_05) {
1082 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1083 ocp_data &= ~ECM_ALDPS;
1084 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1085
1086 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1087 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1088 ocp_data &= ~DYNAMIC_BURST;
1089 else
1090 ocp_data |= DYNAMIC_BURST;
1091 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1092 } else if (tp->version == RTL_VER_06) {
1093 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1094 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1095 ocp_data &= ~DYNAMIC_BURST;
1096 else
1097 ocp_data |= DYNAMIC_BURST;
1098 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1099 }
1100
1101 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1102 ocp_data |= EP4_FULL_FC;
1103 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1104
1105 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1106 ocp_data &= ~TIMER11_EN;
1107 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1108
1109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1110 ocp_data &= ~LED_MODE_MASK;
1111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1112
1113 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1114 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1115 ocp_data |= LPM_TIMER_500MS;
1116 else
1117 ocp_data |= LPM_TIMER_500US;
1118 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1119
1120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1121 ocp_data &= ~SEN_VAL_MASK;
1122 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1123 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1124
1125 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1126
1127 r8153_power_cut_en(tp, false);
1128
1129 r8152b_enable_fc(tp);
1130 rtl_tally_reset(tp);
1131}
1132
1133static void rtl8152_unload(struct r8152 *tp)
1134{
1135 if (tp->version != RTL_VER_01)
1136 r8152_power_cut_en(tp, true);
1137}
1138
1139static void rtl8153_unload(struct r8152 *tp)
1140{
1141 r8153_power_cut_en(tp, false);
1142}
1143
1144static int rtl_ops_init(struct r8152 *tp)
1145{
1146 struct rtl_ops *ops = &tp->rtl_ops;
1147 int ret = 0;
1148
1149 switch (tp->version) {
1150 case RTL_VER_01:
1151 case RTL_VER_02:
1152 case RTL_VER_07:
1153 ops->init = r8152b_init;
1154 ops->enable = rtl8152_enable;
1155 ops->disable = rtl8152_disable;
1156 ops->up = rtl8152_up;
1157 ops->down = rtl8152_down;
1158 ops->unload = rtl8152_unload;
1159 break;
1160
1161 case RTL_VER_03:
1162 case RTL_VER_04:
1163 case RTL_VER_05:
1164 case RTL_VER_06:
1165 ops->init = r8153_init;
1166 ops->enable = rtl8153_enable;
1167 ops->disable = rtl8153_disable;
1168 ops->up = rtl8153_up;
1169 ops->down = rtl8153_down;
1170 ops->unload = rtl8153_unload;
1171 break;
1172
1173 default:
1174 ret = -ENODEV;
1175 printf("r8152 Unknown Device\n");
1176 break;
1177 }
1178
1179 return ret;
1180}
1181
Stefan Roese47c50972016-06-29 07:58:05 +02001182static int r8152_init_common(struct r8152 *tp)
Ted Chen9b6dbd42016-01-20 14:24:52 +08001183{
Ted Chen9b6dbd42016-01-20 14:24:52 +08001184 u8 speed;
1185 int timeout = 0;
1186 int link_detected;
1187
1188 debug("** %s()\n", __func__);
1189
1190 do {
1191 speed = rtl8152_get_speed(tp);
1192
1193 link_detected = speed & LINK_STATUS;
1194 if (!link_detected) {
1195 if (timeout == 0)
1196 printf("Waiting for Ethernet connection... ");
1197 mdelay(TIMEOUT_RESOLUTION);
1198 timeout += TIMEOUT_RESOLUTION;
1199 }
1200 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1201 if (link_detected) {
1202 tp->rtl_ops.enable(tp);
1203
1204 if (timeout != 0)
1205 printf("done.\n");
1206 } else {
1207 printf("unable to connect.\n");
1208 }
1209
1210 return 0;
1211}
1212
Stefan Roese47c50972016-06-29 07:58:05 +02001213static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
Ted Chen9b6dbd42016-01-20 14:24:52 +08001214{
Stefan Roese47c50972016-06-29 07:58:05 +02001215 struct usb_device *udev = ueth->pusb_dev;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001216 u32 opts1, opts2 = 0;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001217 int err;
Ted Chen9b6dbd42016-01-20 14:24:52 +08001218 int actual_len;
1219 unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
1220 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1221
1222 debug("** %s(), len %d\n", __func__, length);
1223
1224 opts1 = length | TX_FS | TX_LS;
1225
1226 tx_desc->opts2 = cpu_to_le32(opts2);
1227 tx_desc->opts1 = cpu_to_le32(opts1);
1228
1229 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1230
Stefan Roese47c50972016-06-29 07:58:05 +02001231 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1232 (void *)msg, length + sizeof(struct tx_desc),
1233 &actual_len, USB_BULK_SEND_TIMEOUT);
Ted Chen9b6dbd42016-01-20 14:24:52 +08001234 debug("Tx: len = %zu, actual = %u, err = %d\n",
1235 length + sizeof(struct tx_desc), actual_len, err);
1236
1237 return err;
1238}
1239
Stefan Roese47c50972016-06-29 07:58:05 +02001240#ifndef CONFIG_DM_ETH
1241static int r8152_init(struct eth_device *eth, bd_t *bd)
1242{
1243 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1244 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1245
1246 return r8152_init_common(tp);
1247}
1248
1249static int r8152_send(struct eth_device *eth, void *packet, int length)
1250{
1251 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1252
1253 return r8152_send_common(dev, packet, length);
1254}
1255
Ted Chen9b6dbd42016-01-20 14:24:52 +08001256static int r8152_recv(struct eth_device *eth)
1257{
1258 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1259
1260 static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
1261 unsigned char *pkt_ptr;
1262 int err;
1263 int actual_len;
1264 u16 packet_len;
1265
1266 u32 bytes_process = 0;
1267 struct rx_desc *rx_desc;
1268
1269 debug("** %s()\n", __func__);
1270
1271 err = usb_bulk_msg(dev->pusb_dev,
1272 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1273 (void *)recv_buf,
1274 RTL8152_AGG_BUF_SZ,
1275 &actual_len,
1276 USB_BULK_RECV_TIMEOUT);
1277 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1278 actual_len, err);
1279 if (err != 0) {
1280 debug("Rx: failed to receive\n");
1281 return -1;
1282 }
1283 if (actual_len > RTL8152_AGG_BUF_SZ) {
1284 debug("Rx: received too many bytes %d\n", actual_len);
1285 return -1;
1286 }
1287
1288 while (bytes_process < actual_len) {
1289 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1290 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1291
1292 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1293 packet_len -= CRC_SIZE;
1294
1295 net_process_received_packet(pkt_ptr, packet_len);
1296
1297 bytes_process +=
1298 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1299
1300 if (bytes_process % 8)
1301 bytes_process = bytes_process + 8 - (bytes_process % 8);
1302 }
1303
1304 return 0;
1305}
1306
1307static void r8152_halt(struct eth_device *eth)
1308{
1309 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1310 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1311
1312 debug("** %s()\n", __func__);
1313
1314 tp->rtl_ops.disable(tp);
1315}
1316
1317static int r8152_write_hwaddr(struct eth_device *eth)
1318{
1319 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1320 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1321
1322 unsigned char enetaddr[8] = {0};
1323
1324 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1325
1326 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1327 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1328 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1329
1330 debug("MAC %pM\n", eth->enetaddr);
1331 return 0;
1332}
1333
1334void r8152_eth_before_probe(void)
1335{
1336 curr_eth_dev = 0;
1337}
1338
1339/* Probe to see if a new device is actually an realtek device */
1340int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1341 struct ueth_data *ss)
1342{
1343 struct usb_interface *iface;
1344 struct usb_interface_descriptor *iface_desc;
1345 int ep_in_found = 0, ep_out_found = 0;
1346 int i;
1347
1348 struct r8152 *tp;
1349
1350 /* let's examine the device now */
1351 iface = &dev->config.if_desc[ifnum];
1352 iface_desc = &dev->config.if_desc[ifnum].desc;
1353
1354 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1355 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1356 dev->descriptor.idProduct == r8152_dongles[i].product)
1357 /* Found a supported dongle */
1358 break;
1359 }
1360
1361 if (i == ARRAY_SIZE(r8152_dongles))
1362 return 0;
1363
1364 memset(ss, 0, sizeof(struct ueth_data));
1365
1366 /* At this point, we know we've got a live one */
1367 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1368 dev->descriptor.idVendor, dev->descriptor.idProduct);
1369
1370 /* Initialize the ueth_data structure with some useful info */
1371 ss->ifnum = ifnum;
1372 ss->pusb_dev = dev;
1373 ss->subclass = iface_desc->bInterfaceSubClass;
1374 ss->protocol = iface_desc->bInterfaceProtocol;
1375
1376 /* alloc driver private */
1377 ss->dev_priv = calloc(1, sizeof(struct r8152));
1378
1379 if (!ss->dev_priv)
1380 return 0;
1381
1382 /*
1383 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1384 * int. We will ignore any others.
1385 */
1386 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1387 /* is it an BULK endpoint? */
1388 if ((iface->ep_desc[i].bmAttributes &
1389 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1390 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1391 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1392 ss->ep_in = ep_addr &
1393 USB_ENDPOINT_NUMBER_MASK;
1394 ep_in_found = 1;
1395 } else {
1396 if (!ep_out_found) {
1397 ss->ep_out = ep_addr &
1398 USB_ENDPOINT_NUMBER_MASK;
1399 ep_out_found = 1;
1400 }
1401 }
1402 }
1403
1404 /* is it an interrupt endpoint? */
1405 if ((iface->ep_desc[i].bmAttributes &
1406 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1407 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1408 USB_ENDPOINT_NUMBER_MASK;
1409 ss->irqinterval = iface->ep_desc[i].bInterval;
1410 }
1411 }
1412
1413 debug("Endpoints In %d Out %d Int %d\n",
1414 ss->ep_in, ss->ep_out, ss->ep_int);
1415
1416 /* Do some basic sanity checks, and bail if we find a problem */
1417 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1418 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1419 debug("Problems with device\n");
1420 return 0;
1421 }
1422
1423 dev->privptr = (void *)ss;
1424
1425 tp = ss->dev_priv;
1426 tp->udev = dev;
1427 tp->intf = iface;
1428
1429 r8152b_get_version(tp);
1430
1431 if (rtl_ops_init(tp))
1432 return 0;
1433
1434 tp->rtl_ops.init(tp);
1435 tp->rtl_ops.up(tp);
1436
1437 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1438 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1439 DUPLEX_FULL);
1440
1441 return 1;
1442}
1443
1444int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1445 struct eth_device *eth)
1446{
1447 if (!eth) {
1448 debug("%s: missing parameter.\n", __func__);
1449 return 0;
1450 }
1451
1452 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1453 eth->init = r8152_init;
1454 eth->send = r8152_send;
1455 eth->recv = r8152_recv;
1456 eth->halt = r8152_halt;
1457 eth->write_hwaddr = r8152_write_hwaddr;
1458 eth->priv = ss;
1459
1460 /* Get the MAC address */
1461 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1462 return 0;
1463
1464 debug("MAC %pM\n", eth->enetaddr);
1465 return 1;
1466}
Stefan Roese47c50972016-06-29 07:58:05 +02001467#endif /* !CONFIG_DM_ETH */
1468
1469#ifdef CONFIG_DM_ETH
1470static int r8152_eth_start(struct udevice *dev)
1471{
1472 struct r8152 *tp = dev_get_priv(dev);
1473
1474 debug("** %s (%d)\n", __func__, __LINE__);
1475
1476 return r8152_init_common(tp);
1477}
1478
1479void r8152_eth_stop(struct udevice *dev)
1480{
1481 struct r8152 *tp = dev_get_priv(dev);
1482
1483 debug("** %s (%d)\n", __func__, __LINE__);
1484
1485 tp->rtl_ops.disable(tp);
1486}
1487
1488int r8152_eth_send(struct udevice *dev, void *packet, int length)
1489{
1490 struct r8152 *tp = dev_get_priv(dev);
1491
1492 return r8152_send_common(&tp->ueth, packet, length);
1493}
1494
1495int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1496{
1497 struct r8152 *tp = dev_get_priv(dev);
1498 struct ueth_data *ueth = &tp->ueth;
1499 uint8_t *ptr;
1500 int ret, len;
1501 struct rx_desc *rx_desc;
1502 u16 packet_len;
1503
1504 len = usb_ether_get_rx_bytes(ueth, &ptr);
1505 debug("%s: first try, len=%d\n", __func__, len);
1506 if (!len) {
1507 if (!(flags & ETH_RECV_CHECK_DEVICE))
1508 return -EAGAIN;
1509 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1510 if (ret)
1511 return ret;
1512
1513 len = usb_ether_get_rx_bytes(ueth, &ptr);
1514 debug("%s: second try, len=%d\n", __func__, len);
1515 }
1516
1517 rx_desc = (struct rx_desc *)ptr;
1518 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1519 packet_len -= CRC_SIZE;
1520
1521 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1522 debug("Rx: too large packet: %d\n", packet_len);
1523 goto err;
1524 }
1525
1526 *packetp = ptr + sizeof(struct rx_desc);
1527 return packet_len;
1528
1529err:
1530 usb_ether_advance_rxbuf(ueth, -1);
1531 return -ENOSPC;
1532}
1533
1534static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1535{
1536 struct r8152 *tp = dev_get_priv(dev);
1537
1538 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1539 packet_len = ALIGN(packet_len, 8);
1540 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1541
1542 return 0;
1543}
1544
1545static int r8152_write_hwaddr(struct udevice *dev)
1546{
1547 struct eth_pdata *pdata = dev_get_platdata(dev);
1548 struct r8152 *tp = dev_get_priv(dev);
1549
1550 unsigned char enetaddr[8] = { 0 };
1551
1552 debug("** %s (%d)\n", __func__, __LINE__);
1553 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1554
1555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1556 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1557 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1558
1559 debug("MAC %pM\n", pdata->enetaddr);
1560 return 0;
1561}
1562
1563int r8152_read_rom_hwaddr(struct udevice *dev)
1564{
1565 struct eth_pdata *pdata = dev_get_platdata(dev);
1566 struct r8152 *tp = dev_get_priv(dev);
1567
1568 debug("** %s (%d)\n", __func__, __LINE__);
1569 r8152_read_mac(tp, pdata->enetaddr);
1570 return 0;
1571}
1572
1573static int r8152_eth_probe(struct udevice *dev)
1574{
1575 struct usb_device *udev = dev_get_parent_priv(dev);
1576 struct eth_pdata *pdata = dev_get_platdata(dev);
1577 struct r8152 *tp = dev_get_priv(dev);
1578 struct ueth_data *ueth = &tp->ueth;
1579 int ret;
1580
1581 tp->udev = udev;
1582 r8152_read_mac(tp, pdata->enetaddr);
1583
1584 r8152b_get_version(tp);
1585
1586 ret = rtl_ops_init(tp);
1587 if (ret)
1588 return ret;
1589
1590 tp->rtl_ops.init(tp);
1591 tp->rtl_ops.up(tp);
1592
1593 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1594 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1595 DUPLEX_FULL);
1596
1597 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1598}
1599
1600static const struct eth_ops r8152_eth_ops = {
1601 .start = r8152_eth_start,
1602 .send = r8152_eth_send,
1603 .recv = r8152_eth_recv,
1604 .free_pkt = r8152_free_pkt,
1605 .stop = r8152_eth_stop,
1606 .write_hwaddr = r8152_write_hwaddr,
1607 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1608};
1609
1610U_BOOT_DRIVER(r8152_eth) = {
1611 .name = "r8152_eth",
1612 .id = UCLASS_ETH,
1613 .probe = r8152_eth_probe,
1614 .ops = &r8152_eth_ops,
1615 .priv_auto_alloc_size = sizeof(struct r8152),
1616 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1617};
1618
1619static const struct usb_device_id r8152_eth_id_table[] = {
1620 /* Realtek */
1621 { USB_DEVICE(0x0bda, 0x8050) },
1622 { USB_DEVICE(0x0bda, 0x8152) },
1623 { USB_DEVICE(0x0bda, 0x8153) },
1624
1625 /* Samsung */
1626 { USB_DEVICE(0x04e8, 0xa101) },
1627
1628 /* Lenovo */
1629 { USB_DEVICE(0x17ef, 0x304f) },
1630 { USB_DEVICE(0x17ef, 0x3052) },
1631 { USB_DEVICE(0x17ef, 0x3054) },
1632 { USB_DEVICE(0x17ef, 0x3057) },
1633 { USB_DEVICE(0x17ef, 0x7205) },
1634 { USB_DEVICE(0x17ef, 0x720a) },
1635 { USB_DEVICE(0x17ef, 0x720b) },
1636 { USB_DEVICE(0x17ef, 0x720c) },
1637
1638 /* TP-LINK */
1639 { USB_DEVICE(0x2357, 0x0601) },
1640
1641 /* Nvidia */
1642 { USB_DEVICE(0x0955, 0x09ff) },
1643
1644 { } /* Terminating entry */
1645};
1646
1647U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1648#endif /* CONFIG_DM_ETH */
1649