Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Qualcomm SDHCI driver - SD/eMMC controller |
| 3 | * |
| 4 | * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
| 5 | * |
| 6 | * Based on Linux driver |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <clk.h> |
| 13 | #include <dm.h> |
| 14 | #include <sdhci.h> |
| 15 | #include <wait_bit.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <linux/bitops.h> |
| 18 | |
| 19 | /* Non-standard registers needed for SDHCI startup */ |
| 20 | #define SDCC_MCI_POWER 0x0 |
| 21 | #define SDCC_MCI_POWER_SW_RST BIT(7) |
| 22 | |
| 23 | /* This is undocumented register */ |
| 24 | #define SDCC_MCI_VERSION 0x50 |
| 25 | #define SDCC_MCI_VERSION_MAJOR_SHIFT 28 |
| 26 | #define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT) |
| 27 | #define SDCC_MCI_VERSION_MINOR_MASK 0xff |
| 28 | |
| 29 | #define SDCC_MCI_STATUS2 0x6C |
| 30 | #define SDCC_MCI_STATUS2_MCI_ACT 0x1 |
| 31 | #define SDCC_MCI_HC_MODE 0x78 |
| 32 | |
| 33 | /* Offset to SDHCI registers */ |
| 34 | #define SDCC_SDHCI_OFFSET 0x900 |
| 35 | |
| 36 | /* Non standard (?) SDHCI register */ |
| 37 | #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c |
| 38 | |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 39 | struct msm_sdhc_plat { |
| 40 | struct mmc_config cfg; |
| 41 | struct mmc mmc; |
| 42 | }; |
| 43 | |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 44 | struct msm_sdhc { |
| 45 | struct sdhci_host host; |
| 46 | void *base; |
| 47 | }; |
| 48 | |
| 49 | DECLARE_GLOBAL_DATA_PTR; |
| 50 | |
| 51 | static int msm_sdc_clk_init(struct udevice *dev) |
| 52 | { |
| 53 | uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, |
| 54 | "clock-frequency", 400000); |
| 55 | uint clkd[2]; /* clk_id and clk_no */ |
| 56 | int clk_offset; |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 57 | struct udevice *clk_dev; |
| 58 | struct clk clk; |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 59 | int ret; |
| 60 | |
| 61 | ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, |
| 62 | 2); |
| 63 | if (ret) |
| 64 | return ret; |
| 65 | |
| 66 | clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); |
| 67 | if (clk_offset < 0) |
| 68 | return clk_offset; |
| 69 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 70 | ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 71 | if (ret) |
| 72 | return ret; |
| 73 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 74 | clk.id = clkd[1]; |
| 75 | ret = clk_request(clk_dev, &clk); |
| 76 | if (ret < 0) |
| 77 | return ret; |
| 78 | |
| 79 | ret = clk_set_rate(&clk, clk_rate); |
| 80 | clk_free(&clk); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 81 | if (ret < 0) |
| 82 | return ret; |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | static int msm_sdc_probe(struct udevice *dev) |
| 88 | { |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 89 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 90 | struct msm_sdhc_plat *plat = dev_get_platdata(dev); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 91 | struct msm_sdhc *prv = dev_get_priv(dev); |
| 92 | struct sdhci_host *host = &prv->host; |
| 93 | u32 core_version, core_minor, core_major; |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 94 | u32 caps; |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 95 | int ret; |
| 96 | |
| 97 | host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; |
| 98 | |
| 99 | /* Init clocks */ |
| 100 | ret = msm_sdc_clk_init(dev); |
| 101 | if (ret) |
| 102 | return ret; |
| 103 | |
| 104 | /* Reset the core and Enable SDHC mode */ |
| 105 | writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST, |
| 106 | prv->base + SDCC_MCI_POWER); |
| 107 | |
| 108 | |
| 109 | /* Wait for reset to be written to register */ |
| 110 | if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2, |
| 111 | SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) { |
| 112 | printf("msm_sdhci: reset request failed\n"); |
| 113 | return -EIO; |
| 114 | } |
| 115 | |
| 116 | /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ |
| 117 | if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER, |
| 118 | SDCC_MCI_POWER_SW_RST, false, 2, false)) { |
| 119 | printf("msm_sdhci: stuck in reset\n"); |
| 120 | return -ETIMEDOUT; |
| 121 | } |
| 122 | |
| 123 | /* Enable host-controller mode */ |
| 124 | writel(1, prv->base + SDCC_MCI_HC_MODE); |
| 125 | |
| 126 | core_version = readl(prv->base + SDCC_MCI_VERSION); |
| 127 | |
| 128 | core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK); |
| 129 | core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT; |
| 130 | |
| 131 | core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK; |
| 132 | |
| 133 | /* |
| 134 | * Support for some capabilities is not advertised by newer |
| 135 | * controller versions and must be explicitly enabled. |
| 136 | */ |
| 137 | if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 138 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 139 | caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; |
| 140 | writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); |
| 141 | } |
| 142 | |
| 143 | /* Set host controller version */ |
| 144 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
| 145 | |
Jaehoon Chung | 8a5ffbb | 2016-07-26 19:06:24 +0900 | [diff] [blame] | 146 | ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 147 | host->mmc = &plat->mmc; |
Mateusz Kulikowski | c012e57 | 2016-06-26 22:43:55 +0200 | [diff] [blame] | 148 | if (ret) |
| 149 | return ret; |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 150 | host->mmc->priv = &prv->host; |
Mateusz Kulikowski | c012e57 | 2016-06-26 22:43:55 +0200 | [diff] [blame] | 151 | host->mmc->dev = dev; |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 152 | upriv->mmc = host->mmc; |
Mateusz Kulikowski | c012e57 | 2016-06-26 22:43:55 +0200 | [diff] [blame] | 153 | |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 154 | return sdhci_probe(dev); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static int msm_sdc_remove(struct udevice *dev) |
| 158 | { |
| 159 | struct msm_sdhc *priv = dev_get_priv(dev); |
| 160 | |
| 161 | /* Disable host-controller mode */ |
| 162 | writel(0, priv->base + SDCC_MCI_HC_MODE); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static int msm_ofdata_to_platdata(struct udevice *dev) |
| 168 | { |
| 169 | struct udevice *parent = dev->parent; |
| 170 | struct msm_sdhc *priv = dev_get_priv(dev); |
| 171 | struct sdhci_host *host = &priv->host; |
| 172 | |
| 173 | host->name = strdup(dev->name); |
| 174 | host->ioaddr = (void *)dev_get_addr(dev); |
| 175 | host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
| 176 | "bus-width", 4); |
| 177 | host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0); |
| 178 | priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, |
| 179 | parent->of_offset, |
| 180 | dev->of_offset, |
Stephen Warren | 7d30e10 | 2016-08-05 09:47:51 -0600 | [diff] [blame] | 181 | "reg", 1, NULL, |
| 182 | false); |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 183 | if (priv->base == (void *)FDT_ADDR_T_NONE || |
| 184 | host->ioaddr == (void *)FDT_ADDR_T_NONE) |
| 185 | return -EINVAL; |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 190 | static int msm_sdc_bind(struct udevice *dev) |
| 191 | { |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 192 | struct msm_sdhc_plat *plat = dev_get_platdata(dev); |
| 193 | int ret; |
| 194 | |
| 195 | ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); |
| 196 | if (ret) |
| 197 | return ret; |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 202 | static const struct udevice_id msm_mmc_ids[] = { |
| 203 | { .compatible = "qcom,sdhci-msm-v4" }, |
| 204 | { } |
| 205 | }; |
| 206 | |
| 207 | U_BOOT_DRIVER(msm_sdc_drv) = { |
| 208 | .name = "msm_sdc", |
| 209 | .id = UCLASS_MMC, |
| 210 | .of_match = msm_mmc_ids, |
| 211 | .ofdata_to_platdata = msm_ofdata_to_platdata, |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 212 | .ops = &sdhci_ops, |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 213 | .bind = msm_sdc_bind, |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 214 | .probe = msm_sdc_probe, |
| 215 | .remove = msm_sdc_remove, |
| 216 | .priv_auto_alloc_size = sizeof(struct msm_sdhc), |
Simon Glass | 8ef0765 | 2016-06-12 23:30:29 -0600 | [diff] [blame] | 217 | .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), |
Mateusz Kulikowski | a00b0c0 | 2016-03-31 23:12:16 +0200 | [diff] [blame] | 218 | }; |