| Masahiro Yamada | 408dd77 | 2016-03-18 16:41:51 +0900 | [diff] [blame] | 1 | /* |
| 2 | * UniPhier SC (System Control) block registers for ARMv8 SoCs |
| 3 | * |
| Masahiro Yamada | d11b0b7 | 2016-09-17 03:33:11 +0900 | [diff] [blame] | 4 | * Copyright (C) 2016 Socionext Inc. |
| 5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
| Masahiro Yamada | 408dd77 | 2016-03-18 16:41:51 +0900 | [diff] [blame] | 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef SC64_REGS_H |
| 11 | #define SC64_REGS_H |
| 12 | |
| 13 | #define SC_BASE_ADDR 0x61840000 |
| 14 | |
| Masahiro Yamada | d11b0b7 | 2016-09-17 03:33:11 +0900 | [diff] [blame] | 15 | /* PLL type: SSC */ |
| 16 | #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD20: CPU/ARM */ |
| 17 | #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD20: misc */ |
| 18 | #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ |
| 19 | #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD20: Video codec */ |
| 20 | #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ |
| 21 | #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ |
| 22 | #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ |
| 23 | #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ |
| 24 | #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ |
| 25 | |
| 26 | /* PLL type: VPLL27 */ |
| 27 | #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) |
| 28 | #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) |
| 29 | |
| 30 | /* PLL type: DSPLL */ |
| 31 | #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) |
| 32 | #define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) |
| 33 | |
| Masahiro Yamada | 408dd77 | 2016-03-18 16:41:51 +0900 | [diff] [blame] | 34 | #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) |
| 35 | #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) |
| 36 | #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) |
| 37 | #define SC_RSTCTRL4_ETHER (1 << 6) |
| 38 | #define SC_RSTCTRL4_NAND (1 << 0) |
| 39 | #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) |
| 40 | #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) |
| 41 | #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) |
| 42 | #define SC_RSTCTRL7_UMCSB (1 << 16) |
| 43 | #define SC_RSTCTRL7_UMCA2 (1 << 10) |
| 44 | #define SC_RSTCTRL7_UMCA1 (1 << 9) |
| 45 | #define SC_RSTCTRL7_UMCA0 (1 << 8) |
| 46 | #define SC_RSTCTRL7_UMC32 (1 << 2) |
| 47 | #define SC_RSTCTRL7_UMC31 (1 << 1) |
| 48 | #define SC_RSTCTRL7_UMC30 (1 << 0) |
| 49 | |
| 50 | #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) |
| 51 | #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) |
| 52 | #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) |
| 53 | #define SC_CLKCTRL4_PERI (1 << 7) |
| 54 | #define SC_CLKCTRL4_ETHER (1 << 6) |
| 55 | #define SC_CLKCTRL4_NAND (1 << 0) |
| 56 | #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) |
| 57 | #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) |
| 58 | #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) |
| 59 | #define SC_CLKCTRL7_UMCSB (1 << 16) |
| 60 | #define SC_CLKCTRL7_UMC32 (1 << 2) |
| 61 | #define SC_CLKCTRL7_UMC31 (1 << 1) |
| 62 | #define SC_CLKCTRL7_UMC30 (1 << 0) |
| 63 | |
| 64 | #endif /* SC64_REGS_H */ |