blob: e69efc4dd62a36d41627fa467b29129b602667c6 [file] [log] [blame]
Peng Fan203a2272019-03-05 02:32:49 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <errno.h>
8#include <linux/libfdt.h>
9#include <environment.h>
10#include <asm/io.h>
11#include <asm/gpio.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/sci/sci.h>
14#include <asm/arch/imx8-pins.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/sys_proto.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
21 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
22 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
23 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
24
25static iomux_cfg_t uart0_pads[] = {
26 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
27 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
28};
29
30static void setup_iomux_uart(void)
31{
32 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
33}
34
35int board_early_init_f(void)
36{
37 int ret;
38 /* Set UART0 clock root to 80 MHz */
39 sc_pm_clock_rate_t rate = 80000000;
40
41 /* Power up UART0 */
42 ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
43 if (ret)
44 return ret;
45
46 ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
47 if (ret)
48 return ret;
49
50 /* Enable UART0 clock root */
51 ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
52 if (ret)
53 return ret;
54
55 setup_iomux_uart();
56
57 sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
58
59 return 0;
60}
61
62#if IS_ENABLED(CONFIG_DM_GPIO)
63static void board_gpio_init(void)
64{
65 /* TODO */
66}
67#else
68static inline void board_gpio_init(void) {}
69#endif
70
71#if IS_ENABLED(CONFIG_FEC_MXC)
72#include <miiphy.h>
73
74int board_phy_config(struct phy_device *phydev)
75{
76 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
77 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
78
79 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
80 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
81 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
82 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
83
84 if (phydev->drv->config)
85 phydev->drv->config(phydev);
86
87 return 0;
88}
89#endif
90
91void build_info(void)
92{
93 u32 sc_build = 0, sc_commit = 0;
94
95 /* Get SCFW build and commit id */
96 sc_misc_build_info(-1, &sc_build, &sc_commit);
97 if (!sc_build) {
98 printf("SCFW does not support build info\n");
99 sc_commit = 0; /* Display 0 when the build info is not supported*/
100 }
101 printf("Build: SCFW %x\n", sc_commit);
102}
103
104int checkboard(void)
105{
106 puts("Board: iMX8QM MEK\n");
107
108 build_info();
109 print_bootinfo();
110
111 return 0;
112}
113
114int board_init(void)
115{
116 /* Power up base board */
117 sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
118
119 board_gpio_init();
120
121 return 0;
122}
123
124void detail_board_ddr_info(void)
125{
126 puts("\nDDR ");
127}
128
129/*
130 * Board specific reset that is system reset.
131 */
132void reset_cpu(ulong addr)
133{
134 /* TODO */
135}
136
137#ifdef CONFIG_OF_BOARD_SETUP
138int ft_board_setup(void *blob, bd_t *bd)
139{
140 return 0;
141}
142#endif
143
144int board_mmc_get_env_dev(int devno)
145{
146 return devno;
147}
148
149int board_late_init(void)
150{
151#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
152 env_set("board_name", "MEK");
153 env_set("board_rev", "iMX8QM");
154#endif
155
156 return 0;
157}