Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 |
Mario Six | b489358 | 2018-03-06 08:04:58 +0100 | [diff] [blame] | 4 | * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * Driver for NXP's pca9698 40 bit I2C gpio expander |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <i2c.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 13 | #include <linux/errno.h> |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 14 | #include <pca9698.h> |
| 15 | |
| 16 | /* |
| 17 | * The pca9698 registers |
| 18 | */ |
| 19 | |
| 20 | #define PCA9698_REG_INPUT 0x00 |
| 21 | #define PCA9698_REG_OUTPUT 0x08 |
| 22 | #define PCA9698_REG_POLARITY 0x10 |
| 23 | #define PCA9698_REG_CONFIG 0x18 |
| 24 | |
| 25 | #define PCA9698_BUFFER_SIZE 5 |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 26 | #define PCA9698_GPIO_COUNT 40 |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 27 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 28 | static int pca9698_read40(u8 addr, u8 offset, u8 *buffer) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 29 | { |
| 30 | u8 command = offset | 0x80; /* autoincrement */ |
| 31 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 32 | return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 33 | } |
| 34 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 35 | static int pca9698_write40(u8 addr, u8 offset, u8 *buffer) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 36 | { |
| 37 | u8 command = offset | 0x80; /* autoincrement */ |
| 38 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 39 | return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value) |
| 43 | { |
| 44 | unsigned byte = gpio / 8; |
| 45 | unsigned bit = gpio % 8; |
| 46 | |
| 47 | if (value) |
| 48 | buffer[byte] |= (1 << bit); |
| 49 | else |
| 50 | buffer[byte] &= ~(1 << bit); |
| 51 | } |
| 52 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 53 | int pca9698_request(unsigned gpio, const char *label) |
| 54 | { |
| 55 | if (gpio >= PCA9698_GPIO_COUNT) |
| 56 | return -EINVAL; |
| 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
| 61 | void pca9698_free(unsigned gpio) |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | int pca9698_direction_input(u8 addr, unsigned gpio) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 66 | { |
| 67 | u8 data[PCA9698_BUFFER_SIZE]; |
| 68 | int res; |
| 69 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 70 | res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 71 | if (res) |
| 72 | return res; |
| 73 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 74 | pca9698_set_bit(gpio, data, 1); |
| 75 | |
| 76 | return pca9698_write40(addr, PCA9698_REG_CONFIG, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 79 | int pca9698_direction_output(u8 addr, unsigned gpio, int value) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 80 | { |
| 81 | u8 data[PCA9698_BUFFER_SIZE]; |
| 82 | int res; |
| 83 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 84 | res = pca9698_set_value(addr, gpio, value); |
| 85 | if (res) |
| 86 | return res; |
| 87 | |
| 88 | res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 89 | if (res) |
| 90 | return res; |
| 91 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 92 | pca9698_set_bit(gpio, data, 0); |
| 93 | |
| 94 | return pca9698_write40(addr, PCA9698_REG_CONFIG, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 97 | int pca9698_get_value(u8 addr, unsigned gpio) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 98 | { |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 99 | unsigned config_byte = gpio / 8; |
| 100 | unsigned config_bit = gpio % 8; |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 101 | unsigned value; |
| 102 | u8 data[PCA9698_BUFFER_SIZE]; |
| 103 | int res; |
| 104 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 105 | res = pca9698_read40(addr, PCA9698_REG_INPUT, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 106 | if (res) |
| 107 | return -1; |
| 108 | |
| 109 | value = data[config_byte] & (1 << config_bit); |
| 110 | |
| 111 | return !!value; |
| 112 | } |
| 113 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 114 | int pca9698_set_value(u8 addr, unsigned gpio, int value) |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 115 | { |
| 116 | u8 data[PCA9698_BUFFER_SIZE]; |
| 117 | int res; |
| 118 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 119 | res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 120 | if (res) |
| 121 | return res; |
| 122 | |
Dirk Eibach | bae3a22 | 2011-10-31 09:39:12 +0100 | [diff] [blame] | 123 | pca9698_set_bit(gpio, data, value); |
| 124 | |
| 125 | return pca9698_write40(addr, PCA9698_REG_OUTPUT, data); |
Dirk Eibach | c3213b8 | 2011-10-03 23:13:51 +0000 | [diff] [blame] | 126 | } |