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git01.mediatek.com / filogic / uboot / 800ea3ee42b66c679844bc4e5060ca4e2d80e144 / . / board / actux1 / u-boot.lds
blob: 989ad7121d19a519435b81ef0631ab4d1d21ade8 [file] [log] [blame]
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
25OUTPUT_ARCH (arm)
26ENTRY (_start)
27SECTIONS
28{
29 . = 0x00000000;
30
31 . = ALIGN (4);
32 .text : {
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]33 arch/arm/cpu/ixp/start.o(.text*)
34 net/libnet.o(.text*)
35 board/actux1/libactux1.o(.text*)
36 arch/arm/cpu/ixp/libixp.o(.text*)
Tom Rinia8381c92012-10-17 10:18:29 +0000[diff] [blame]37 drivers/input/libinput.o(.text*)
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]38
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]39 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]40 common/env_embedded.o(.ppcenv)
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]41 *(.text*)
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]42 }
43
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]44 . = ALIGN(4);
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]45 .rodata : {
Trent Piepho4438e5e2009-02-18 15:22:05 -0800[diff] [blame]46 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]47 }
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]48 . = ALIGN(4);
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]49 .data : {
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]50 *(.data*)
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]51 }
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]52 . = ALIGN(4);
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]53 .got : {
54 *(.got)
55 }
56 . =.;
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]57
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]58 . = ALIGN(4);
59 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]60 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]61 }
62
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]63 . = ALIGN (4);
Benoît Thébaudeau03bae032013-04-11 09:35:46 +0000[diff] [blame]64
65 __image_copy_end = .;
66
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]67 .rel.dyn : {
68 __rel_dyn_start = .;
69 *(.rel*)
70 __rel_dyn_end = .;
71 }
72
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]73 _end = .;
74
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]75/*
76 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
77 * __bss_base and __bss_limit are for linker only (overlay ordering)
78 */
79
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]80 .bss_start __rel_dyn_start (OVERLAY) : {
81 KEEP(*(.__bss_start));
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]82 __bss_base = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]83 }
84
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]85 .bss __bss_base (OVERLAY) : {
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]86 *(.bss*)
87 . = ALIGN(4);
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]88 __bss_limit = .;
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]89 }
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]90 .bss_end __bss_limit (OVERLAY) : {
91 KEEP(*(.__bss_end));
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]92 }
93
Albert ARIBAUD16915932013-06-11 14:17:31 +0200[diff] [blame]94 /DISCARD/ : { *(.dynsym) }
Michael Schwingen5af65842011-05-23 00:00:04 +0200[diff] [blame]95 /DISCARD/ : { *(.dynstr*) }
96 /DISCARD/ : { *(.dynamic*) }
97 /DISCARD/ : { *(.plt*) }
98 /DISCARD/ : { *(.interp*) }
99 /DISCARD/ : { *(.gnu*) }
Michael Schwingen4d56c882008-01-16 19:50:37 +0100[diff] [blame]100}