Oleksandr Andrushchenko | 7fd47cc | 2020-08-06 12:42:46 +0300 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: MIT |
| 2 | * |
| 3 | * params.h |
| 4 | * |
| 5 | * HVM parameters. HVM (Hardware Virtual Machine) is the type of instance |
| 6 | * that mimics bare-metal server setup which provides better hardware |
| 7 | * isolation. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ |
| 11 | #define __XEN_PUBLIC_HVM_PARAMS_H__ |
| 12 | |
| 13 | #include <xen/interface/hvm/hvm_op.h> |
| 14 | |
| 15 | /* |
| 16 | * Parameter space for HVMOP_{set,get}_param. |
| 17 | */ |
| 18 | |
| 19 | #define HVM_PARAM_CALLBACK_IRQ 0 |
| 20 | /* |
| 21 | * How should CPU0 event-channel notifications be delivered? |
| 22 | * |
| 23 | * If val == 0 then CPU0 event-channel notifications are not delivered. |
| 24 | * If val != 0, val[63:56] encodes the type, as follows: |
| 25 | */ |
| 26 | |
| 27 | #define HVM_PARAM_CALLBACK_TYPE_GSI 0 |
| 28 | /* |
| 29 | * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, |
| 30 | * and disables all notifications. |
| 31 | */ |
| 32 | |
| 33 | #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 |
| 34 | /* |
| 35 | * val[55:0] is a delivery PCI INTx line: |
| 36 | * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] |
| 37 | */ |
| 38 | |
| 39 | #if defined(__i386__) || defined(__x86_64__) |
| 40 | #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 |
| 41 | /* |
| 42 | * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know |
| 43 | * if this delivery method is available. |
| 44 | */ |
| 45 | #elif defined(__arm__) || defined(__aarch64__) |
| 46 | #define HVM_PARAM_CALLBACK_TYPE_PPI 2 |
| 47 | /* |
| 48 | * val[55:16] needs to be zero. |
| 49 | * val[15:8] is interrupt flag of the PPI used by event-channel: |
| 50 | * bit 8: the PPI is edge(1) or level(0) triggered |
| 51 | * bit 9: the PPI is active low(1) or high(0) |
| 52 | * val[7:0] is a PPI number used by event-channel. |
| 53 | * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to |
| 54 | * the notification is handled by the interrupt controller. |
| 55 | */ |
| 56 | #endif |
| 57 | |
| 58 | #define HVM_PARAM_STORE_PFN 1 |
| 59 | #define HVM_PARAM_STORE_EVTCHN 2 |
| 60 | |
| 61 | #define HVM_PARAM_PAE_ENABLED 4 |
| 62 | |
| 63 | #define HVM_PARAM_IOREQ_PFN 5 |
| 64 | |
| 65 | #define HVM_PARAM_BUFIOREQ_PFN 6 |
| 66 | |
| 67 | /* |
| 68 | * Set mode for virtual timers (currently x86 only): |
| 69 | * delay_for_missed_ticks (default): |
| 70 | * Do not advance a vcpu's time beyond the correct delivery time for |
| 71 | * interrupts that have been missed due to preemption. Deliver missed |
| 72 | * interrupts when the vcpu is rescheduled and advance the vcpu's virtual |
| 73 | * time stepwise for each one. |
| 74 | * no_delay_for_missed_ticks: |
| 75 | * As above, missed interrupts are delivered, but guest time always tracks |
| 76 | * wallclock (i.e., real) time while doing so. |
| 77 | * no_missed_ticks_pending: |
| 78 | * No missed interrupts are held pending. Instead, to ensure ticks are |
| 79 | * delivered at some non-zero rate, if we detect missed ticks then the |
| 80 | * internal tick alarm is not disabled if the VCPU is preempted during the |
| 81 | * next tick period. |
| 82 | * one_missed_tick_pending: |
| 83 | * Missed interrupts are collapsed together and delivered as one 'late tick'. |
| 84 | * Guest time always tracks wallclock (i.e., real) time. |
| 85 | */ |
| 86 | #define HVM_PARAM_TIMER_MODE 10 |
| 87 | #define HVMPTM_delay_for_missed_ticks 0 |
| 88 | #define HVMPTM_no_delay_for_missed_ticks 1 |
| 89 | #define HVMPTM_no_missed_ticks_pending 2 |
| 90 | #define HVMPTM_one_missed_tick_pending 3 |
| 91 | |
| 92 | /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ |
| 93 | #define HVM_PARAM_HPET_ENABLED 11 |
| 94 | |
| 95 | /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ |
| 96 | #define HVM_PARAM_IDENT_PT 12 |
| 97 | |
| 98 | /* Device Model domain, defaults to 0. */ |
| 99 | #define HVM_PARAM_DM_DOMAIN 13 |
| 100 | |
| 101 | /* ACPI S state: currently support S0 and S3 on x86. */ |
| 102 | #define HVM_PARAM_ACPI_S_STATE 14 |
| 103 | |
| 104 | /* TSS used on Intel when CR0.PE=0. */ |
| 105 | #define HVM_PARAM_VM86_TSS 15 |
| 106 | |
| 107 | /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ |
| 108 | #define HVM_PARAM_VPT_ALIGN 16 |
| 109 | |
| 110 | /* Console debug shared memory ring and event channel */ |
| 111 | #define HVM_PARAM_CONSOLE_PFN 17 |
| 112 | #define HVM_PARAM_CONSOLE_EVTCHN 18 |
| 113 | |
| 114 | #define HVM_NR_PARAMS 19 |
| 115 | |
| 116 | #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ |