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git01.mediatek.com / filogic / uboot / 7fb8ccd1418fe84bc229ffb829164b16e79b838f / . / arch / arm / dts / rk3399-firefly.dts
blob: edf48fbdd4b9011dac203420417de7a7f27a4fc1 [file] [log] [blame]
Kever Yanga46de892017-04-19 18:17:32 +0800[diff] [blame]1/*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8#include <dt-bindings/pwm/pwm.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include "rk3399.dtsi"
11#include "rk3399-sdram-ddr3-1333.dtsi"
12
13/ {
14 model = "Firefly-RK3399 Board";
15 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
16
17 chosen {
18 stdout-path = &uart2;
19 };
20
21 backlight: backlight {
22 compatible = "pwm-backlight";
23 enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
24 pwms = <&pwm0 0 25000 0>;
25 brightness-levels = <
26 0 1 2 3 4 5 6 7
27 8 9 10 11 12 13 14 15
28 16 17 18 19 20 21 22 23
29 24 25 26 27 28 29 30 31
30 32 33 34 35 36 37 38 39
31 40 41 42 43 44 45 46 47
32 48 49 50 51 52 53 54 55
33 56 57 58 59 60 61 62 63
34 64 65 66 67 68 69 70 71
35 72 73 74 75 76 77 78 79
36 80 81 82 83 84 85 86 87
37 88 89 90 91 92 93 94 95
38 96 97 98 99 100 101 102 103
39 104 105 106 107 108 109 110 111
40 112 113 114 115 116 117 118 119
41 120 121 122 123 124 125 126 127
42 128 129 130 131 132 133 134 135
43 136 137 138 139 140 141 142 143
44 144 145 146 147 148 149 150 151
45 152 153 154 155 156 157 158 159
46 160 161 162 163 164 165 166 167
47 168 169 170 171 172 173 174 175
48 176 177 178 179 180 181 182 183
49 184 185 186 187 188 189 190 191
50 192 193 194 195 196 197 198 199
51 200 201 202 203 204 205 206 207
52 208 209 210 211 212 213 214 215
53 216 217 218 219 220 221 222 223
54 224 225 226 227 228 229 230 231
55 232 233 234 235 236 237 238 239
56 240 241 242 243 244 245 246 247
57 248 249 250 251 252 253 254 255>;
58 default-brightness-level = <200>;
59 };
60
61 clkin_gmac: external-gmac-clock {
62 compatible = "fixed-clock";
63 clock-frequency = <125000000>;
64 clock-output-names = "clkin_gmac";
65 #clock-cells = <0>;
66 };
67
68 rt5640-sound {
69 compatible = "simple-audio-card";
70 simple-audio-card,name = "rockchip,rt5640-codec";
71 simple-audio-card,format = "i2s";
72 simple-audio-card,mclk-fs = <256>;
73 simple-audio-card,widgets =
74 "Microphone", "Mic Jack",
75 "Headphone", "Headphone Jack";
76 simple-audio-card,routing =
77 "Mic Jack", "MICBIAS1",
78 "IN1P", "Mic Jack",
79 "Headphone Jack", "HPOL",
80 "Headphone Jack", "HPOR";
81
82 simple-audio-card,cpu {
83 sound-dai = <&i2s1>;
84 };
85
86 simple-audio-card,codec {
87 sound-dai = <&rt5640>;
88 };
89 };
90
91 sdio_pwrseq: sdio-pwrseq {
92 compatible = "mmc-pwrseq-simple";
93 clocks = <&rk808 1>;
94 clock-names = "ext_clock";
95 pinctrl-names = "default";
96 pinctrl-0 = <&wifi_enable_h>;
97
98 /*
99 * On the module itself this is one of these (depending
100 * on the actual card populated):
101 * - SDIO_RESET_L_WL_REG_ON
102 * - PDN (power down when low)
103 */
104 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
105 };
106
107 vcc3v3_pcie: vcc3v3-pcie-regulator {
108 compatible = "regulator-fixed";
109 enable-active-high;
110 gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pcie_drv>;
113 regulator-name = "vcc3v3_pcie";
114 regulator-always-on;
115 regulator-boot-on;
116 };
117
118 vcc3v3_sys: vcc3v3-sys {
119 compatible = "regulator-fixed";
120 regulator-name = "vcc3v3_sys";
121 regulator-always-on;
122 regulator-boot-on;
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
126
127 vcc5v0_host: vcc5v0-host-regulator {
128 compatible = "regulator-fixed";
129 enable-active-high;
130 gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&host_vbus_drv>;
133 regulator-name = "vcc5v0_host";
134 regulator-always-on;
135 };
136
137 vcc5v0_sys: vcc5v0-sys {
138 compatible = "regulator-fixed";
139 regulator-name = "vcc5v0_sys";
140 regulator-always-on;
141 regulator-boot-on;
142 regulator-min-microvolt = <5000000>;
143 regulator-max-microvolt = <5000000>;
144 };
145
146 vcc_phy: vcc-phy-regulator {
147 compatible = "regulator-fixed";
148 regulator-name = "vcc_phy";
149 regulator-always-on;
150 regulator-boot-on;
151 };
152
153 vdd_log: vdd-log {
154 compatible = "pwm-regulator";
155 pwms = <&pwm2 0 25000 1>;
156 regulator-name = "vdd_log";
157 regulator-always-on;
158 regulator-boot-on;
159 regulator-min-microvolt = <800000>;
160 regulator-max-microvolt = <1400000>;
161 };
162
163 vccadc_ref: vccadc-ref {
164 compatible = "regulator-fixed";
165 regulator-name = "vcc1v8_sys";
166 regulator-always-on;
167 regulator-boot-on;
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <1800000>;
170 };
171};
172
173&cpu_l0 {
174 cpu-supply = <&vdd_cpu_l>;
175};
176
177&cpu_l1 {
178 cpu-supply = <&vdd_cpu_l>;
179};
180
181&cpu_l2 {
182 cpu-supply = <&vdd_cpu_l>;
183};
184
185&cpu_l3 {
186 cpu-supply = <&vdd_cpu_l>;
187};
188
189&cpu_b0 {
190 cpu-supply = <&vdd_cpu_b>;
191};
192
193&cpu_b1 {
194 cpu-supply = <&vdd_cpu_b>;
195};
196
197&emmc_phy {
198 status = "okay";
199};
200
201&gmac {
202 assigned-clocks = <&cru SCLK_RMII_SRC>;
203 assigned-clock-parents = <&clkin_gmac>;
204 clock_in_out = "input";
205 phy-supply = <&vcc_phy>;
206 phy-mode = "rgmii";
207 pinctrl-names = "default";
208 pinctrl-0 = <&rgmii_pins>;
209 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
210 snps,reset-active-low;
211 snps,reset-delays-us = <0 10000 50000>;
212 tx_delay = <0x28>;
213 rx_delay = <0x11>;
214 status = "okay";
215};
216
217&i2c0 {
218 clock-frequency = <400000>;
219 i2c-scl-rising-time-ns = <168>;
220 i2c-scl-falling-time-ns = <4>;
221 status = "okay";
222
223 rk808: pmic@1b {
224 compatible = "rockchip,rk808";
225 reg = <0x1b>;
226 interrupt-parent = <&gpio1>;
227 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
228 #clock-cells = <1>;
229 clock-output-names = "xin32k", "rk808-clkout2";
230 pinctrl-names = "default";
231 pinctrl-0 = <&pmic_int_l>;
232 rockchip,system-power-controller;
233 wakeup-source;
234
235 vcc1-supply = <&vcc3v3_sys>;
236 vcc2-supply = <&vcc3v3_sys>;
237 vcc3-supply = <&vcc3v3_sys>;
238 vcc4-supply = <&vcc3v3_sys>;
239 vcc6-supply = <&vcc3v3_sys>;
240 vcc7-supply = <&vcc3v3_sys>;
241 vcc8-supply = <&vcc3v3_sys>;
242 vcc9-supply = <&vcc3v3_sys>;
243 vcc10-supply = <&vcc3v3_sys>;
244 vcc11-supply = <&vcc3v3_sys>;
245 vcc12-supply = <&vcc3v3_sys>;
246 vddio-supply = <&vcc1v8_pmu>;
247
248 regulators {
249 vdd_center: DCDC_REG1 {
250 regulator-name = "vdd_center";
251 regulator-always-on;
252 regulator-boot-on;
253 regulator-min-microvolt = <750000>;
254 regulator-max-microvolt = <1350000>;
255 regulator-ramp-delay = <6001>;
256 regulator-state-mem {
257 regulator-off-in-suspend;
258 };
259 };
260
261 vdd_cpu_l: DCDC_REG2 {
262 regulator-name = "vdd_cpu_l";
263 regulator-always-on;
264 regulator-boot-on;
265 regulator-min-microvolt = <750000>;
266 regulator-max-microvolt = <1350000>;
267 regulator-ramp-delay = <6001>;
268 regulator-state-mem {
269 regulator-off-in-suspend;
270 };
271 };
272
273 vcc_ddr: DCDC_REG3 {
274 regulator-name = "vcc_ddr";
275 regulator-always-on;
276 regulator-boot-on;
277 regulator-state-mem {
278 regulator-on-in-suspend;
279 };
280 };
281
282 vcc_1v8: DCDC_REG4 {
283 regulator-name = "vcc_1v8";
284 regulator-always-on;
285 regulator-boot-on;
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <1800000>;
288 regulator-state-mem {
289 regulator-on-in-suspend;
290 regulator-suspend-microvolt = <1800000>;
291 };
292 };
293
294 vcc1v8_dvp: LDO_REG1 {
295 regulator-name = "vcc1v8_dvp";
296 regulator-always-on;
297 regulator-boot-on;
298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <1800000>;
300 regulator-state-mem {
301 regulator-off-in-suspend;
302 };
303 };
304
305 vcc3v0_tp: LDO_REG2 {
306 regulator-name = "vcc3v0_tp";
307 regulator-always-on;
308 regulator-boot-on;
309 regulator-min-microvolt = <3000000>;
310 regulator-max-microvolt = <3000000>;
311 regulator-state-mem {
312 regulator-off-in-suspend;
313 };
314 };
315
316 vcc1v8_pmu: LDO_REG3 {
317 regulator-name = "vcc1v8_pmu";
318 regulator-always-on;
319 regulator-boot-on;
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <1800000>;
322 regulator-state-mem {
323 regulator-on-in-suspend;
324 regulator-suspend-microvolt = <1800000>;
325 };
326 };
327
328 vcc_sd: LDO_REG4 {
329 regulator-name = "vcc_sd";
330 regulator-always-on;
331 regulator-boot-on;
332 regulator-min-microvolt = <1800000>;
333 regulator-max-microvolt = <3300000>;
334 regulator-state-mem {
335 regulator-on-in-suspend;
336 regulator-suspend-microvolt = <3300000>;
337 };
338 };
339
340 vcca3v0_codec: LDO_REG5 {
341 regulator-name = "vcca3v0_codec";
342 regulator-always-on;
343 regulator-boot-on;
344 regulator-min-microvolt = <3000000>;
345 regulator-max-microvolt = <3000000>;
346 regulator-state-mem {
347 regulator-off-in-suspend;
348 };
349 };
350
351 vcc_1v5: LDO_REG6 {
352 regulator-name = "vcc_1v5";
353 regulator-always-on;
354 regulator-boot-on;
355 regulator-min-microvolt = <1500000>;
356 regulator-max-microvolt = <1500000>;
357 regulator-state-mem {
358 regulator-on-in-suspend;
359 regulator-suspend-microvolt = <1500000>;
360 };
361 };
362
363 vcca1v8_codec: LDO_REG7 {
364 regulator-name = "vcca1v8_codec";
365 regulator-always-on;
366 regulator-boot-on;
367 regulator-min-microvolt = <1800000>;
368 regulator-max-microvolt = <1800000>;
369 regulator-state-mem {
370 regulator-off-in-suspend;
371 };
372 };
373
374 vcc_3v0: LDO_REG8 {
375 regulator-name = "vcc_3v0";
376 regulator-always-on;
377 regulator-boot-on;
378 regulator-min-microvolt = <3000000>;
379 regulator-max-microvolt = <3000000>;
380 regulator-state-mem {
381 regulator-on-in-suspend;
382 regulator-suspend-microvolt = <3000000>;
383 };
384 };
385
386 vcc3v3_s3: SWITCH_REG1 {
387 regulator-name = "vcc3v3_s3";
388 regulator-always-on;
389 regulator-boot-on;
390 regulator-state-mem {
391 regulator-off-in-suspend;
392 };
393 };
394
395 vcc3v3_s0: SWITCH_REG2 {
396 regulator-name = "vcc3v3_s0";
397 regulator-always-on;
398 regulator-boot-on;
399 regulator-state-mem {
400 regulator-off-in-suspend;
401 };
402 };
403 };
404 };
405
406 vdd_cpu_b: regulator@40 {
407 compatible = "silergy,syr827";
408 reg = <0x40>;
409 fcs,suspend-voltage-selector = <0>;
410 regulator-name = "vdd_cpu_b";
411 regulator-min-microvolt = <712500>;
412 regulator-max-microvolt = <1500000>;
413 regulator-ramp-delay = <1000>;
414 regulator-always-on;
415 regulator-boot-on;
416 vin-supply = <&vcc5v0_sys>;
417
418 regulator-state-mem {
419 regulator-off-in-suspend;
420 };
421 };
422
423 vdd_gpu: regulator@41 {
424 compatible = "silergy,syr828";
425 reg = <0x41>;
426 fcs,suspend-voltage-selector = <1>;
427 regulator-name = "vdd_gpu";
428 regulator-min-microvolt = <712500>;
429 regulator-max-microvolt = <1500000>;
430 regulator-ramp-delay = <1000>;
431 regulator-always-on;
432 regulator-boot-on;
433 vin-supply = <&vcc5v0_sys>;
434
435 regulator-state-mem {
436 regulator-off-in-suspend;
437 };
438 };
439};
440
441&i2c1 {
442 i2c-scl-rising-time-ns = <300>;
443 i2c-scl-falling-time-ns = <15>;
444 status = "okay";
445
446 rt5640: rt5640@1c {
447 compatible = "realtek,rt5640";
448 reg = <0x1c>;
449 clocks = <&cru SCLK_I2S_8CH_OUT>;
450 clock-names = "mclk";
451 realtek,in1-differential;
452 #sound-dai-cells = <0>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&rt5640_hpcon>;
455 };
456};
457
458&i2c3 {
459 i2c-scl-rising-time-ns = <450>;
460 i2c-scl-falling-time-ns = <15>;
461 status = "okay";
462};
463
464&i2c4 {
465 i2c-scl-rising-time-ns = <600>;
466 i2c-scl-falling-time-ns = <20>;
467 status = "okay";
468
469 accelerometer@68 {
470 compatible = "invensense,mpu6500";
471 reg = <0x68>;
472 interrupt-parent = <&gpio1>;
473 interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
474 };
475};
476
477&i2s0 {
478 rockchip,playback-channels = <8>;
479 rockchip,capture-channels = <8>;
480 #sound-dai-cells = <0>;
481 status = "okay";
482};
483
484&i2s1 {
485 rockchip,playback-channels = <2>;
486 rockchip,capture-channels = <2>;
487 #sound-dai-cells = <0>;
488 status = "okay";
489};
490
491&i2s2 {
492 #sound-dai-cells = <0>;
493 status = "okay";
494};
495
496&io_domains {
497 status = "okay";
498
499 bt656-supply = <&vcc1v8_dvp>;
500 audio-supply = <&vcca1v8_codec>;
501 sdmmc-supply = <&vcc_sd>;
502 gpio1830-supply = <&vcc_3v0>;
503};
504
505&pcie_phy {
506 status = "okay";
507};
508
509&pcie0 {
510 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
511 num-lanes = <4>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pcie_clkreqn>;
514 status = "okay";
515};
516
517&pmu_io_domains {
518 pmu1830-supply = <&vcc_3v0>;
519 status = "okay";
520};
521
522&pinctrl {
523 buttons {
524 pwrbtn: pwrbtn {
525 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
526 };
527 };
528
529 lcd-panel {
530 lcd_panel_reset: lcd-panel-reset {
531 rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
532 };
533 };
534
535 pcie {
536 pcie_drv: pcie-drv {
537 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
538 };
539
540 pcie_3g_drv: pcie-3g-drv {
541 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
542 };
543 };
544
545 pmic {
546 vsel1_gpio: vsel1-gpio {
547 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
548 };
549
550 vsel2_gpio: vsel2-gpio {
551 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
552 };
553 };
554
555 sdio-pwrseq {
556 wifi_enable_h: wifi-enable-h {
557 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
558 };
559 };
560
561 rt5640 {
562 rt5640_hpcon: rt5640-hpcon {
563 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
564 };
565 };
566
567 pmic {
568 pmic_int_l: pmic-int-l {
569 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
570 };
571 };
572
573 usb2 {
574 host_vbus_drv: host-vbus-drv {
575 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
576 };
577 };
578};
579
580&pwm0 {
581 status = "okay";
582};
583
584&pwm2 {
585 status = "okay";
586};
587
588&saradc {
589 vref-supply = <&vccadc_ref>;
590 status = "okay";
591};
592
593&sdhci {
594 bus-width = <8>;
595 keep-power-in-suspend;
596 mmc-hs400-1_8v;
597 mmc-hs400-enhanced-strobe;
598 non-removable;
599 status = "okay";
600};
601
602&tsadc {
603 /* tshut mode 0:CRU 1:GPIO */
604 rockchip,hw-tshut-mode = <1>;
605 /* tshut polarity 0:LOW 1:HIGH */
606 rockchip,hw-tshut-polarity = <1>;
607 status = "okay";
608};
609
610&u2phy0 {
611 status = "okay";
612
613 u2phy0_otg: otg-port {
614 status = "okay";
615 };
616
617 u2phy0_host: host-port {
618 phy-supply = <&vcc5v0_host>;
619 status = "okay";
620 };
621};
622
623&u2phy1 {
624 status = "okay";
625
626 u2phy1_otg: otg-port {
627 status = "okay";
628 };
629
630 u2phy1_host: host-port {
631 phy-supply = <&vcc5v0_host>;
632 status = "okay";
633 };
634};
635
636&uart0 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&uart0_xfer &uart0_cts>;
639 status = "okay";
640};
641
642&uart2 {
643 status = "okay";
644};
645
646&usb_host0_ehci {
647 status = "okay";
648};
649
650&usb_host0_ohci {
651 status = "okay";
652};
653
654&usb_host1_ehci {
655 status = "okay";
656};
657
658&usb_host1_ohci {
659 status = "okay";
660};