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David Brownell7a846182009-05-15 23:48:37 +02001/*
2 * Copyright (C) 2009 David Brownell
3 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
David Brownell7a846182009-05-15 23:48:37 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
David Brownell7a846182009-05-15 23:48:37 +02009
10/* Spectrum Digital TMS320DM355 EVM board */
11#define DAVINCI_DM355EVM
12
13#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
David Brownell7a846182009-05-15 23:48:37 +020014#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
15#define CONFIG_SYS_CONSOLE_INFO_QUIET
David Brownell7a846182009-05-15 23:48:37 +020016
17/* SoC Configuration */
David Brownell7a846182009-05-15 23:48:37 +020018#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
19#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
David Brownell7a846182009-05-15 23:48:37 +020020#define CONFIG_SOC_DM355
21
22/* Memory Info */
23#define CONFIG_NR_DRAM_BANKS 1
24#define PHYS_SDRAM_1 0x80000000
Sandeep Paulraj391d1a62009-09-08 17:09:52 -040025#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
David Brownell7a846182009-05-15 23:48:37 +020026
27/* Serial Driver info: UART0 for console */
28#define CONFIG_SYS_NS16550
29#define CONFIG_SYS_NS16550_SERIAL
30#define CONFIG_SYS_NS16550_REG_SIZE -4
31#define CONFIG_SYS_NS16550_COM1 0x01c20000
32#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
David Brownell7a846182009-05-15 23:48:37 +020033#define CONFIG_CONS_INDEX 1
34#define CONFIG_BAUDRATE 115200
35
36/* Ethernet: external DM9000 */
37#define CONFIG_DRIVER_DM9000 1
38#define CONFIG_DM9000_BASE 0x04014000
39#define DM9000_IO CONFIG_DM9000_BASE
40#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
David Brownell7a846182009-05-15 23:48:37 +020041
42/* I2C */
Vitaly Andrianovbc9cd952014-04-04 13:16:52 -040043#define CONFIG_SYS_I2C
44#define CONFIG_SYS_I2C_DAVINCI
45#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
46#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
David Brownell7a846182009-05-15 23:48:37 +020047
48/* NAND: socketed, two chipselects, normally 2 GBytes */
Sandeep Paulraj832b9152009-09-08 18:08:06 -040049#define CONFIG_NAND_DAVINCI
Nick Thompson789c8872009-12-12 12:12:26 -050050#define CONFIG_SYS_NAND_CS 2
David Brownell7a846182009-05-15 23:48:37 +020051#define CONFIG_SYS_NAND_USE_FLASH_BBT
Sandeep Paulraj832b9152009-09-08 18:08:06 -040052#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
53#define CONFIG_SYS_NAND_PAGE_2K
David Brownell7a846182009-05-15 23:48:37 +020054
55#define CONFIG_SYS_NAND_LARGEPAGE
56#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
57/* socket has two chipselects, nCE0 gated by address BIT(14) */
58#define CONFIG_SYS_MAX_NAND_DEVICE 1
59#define CONFIG_SYS_NAND_MAX_CHIPS 2
60
Sandeep Paulrajee0e6632010-12-18 18:14:49 -050061/* SD/MMC */
62#define CONFIG_MMC
63#define CONFIG_GENERIC_MMC
64#define CONFIG_DAVINCI_MMC
65#define CONFIG_DAVINCI_MMC_SD1
66#define CONFIG_MMC_MBLOCK
67
David Brownell7a846182009-05-15 23:48:37 +020068/* USB: OTG connector */
69/* NYET -- #define CONFIG_USB_DAVINCI */
70
71/* U-Boot command configuration */
David Brownell7a846182009-05-15 23:48:37 +020072#define CONFIG_CMD_ASKENV
73#define CONFIG_CMD_DHCP
74#define CONFIG_CMD_I2C
75#define CONFIG_CMD_PING
76#define CONFIG_CMD_SAVES
77
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +000078#ifdef CONFIG_CMD_BDI
79#define CONFIG_CLOCKS
80#endif
81
Sandeep Paulrajee0e6632010-12-18 18:14:49 -050082#ifdef CONFIG_MMC
83#define CONFIG_DOS_PARTITION
84#define CONFIG_CMD_EXT2
85#define CONFIG_CMD_FAT
86#define CONFIG_CMD_MMC
87#endif
88
David Brownell7a846182009-05-15 23:48:37 +020089#ifdef CONFIG_NAND_DAVINCI
90#define CONFIG_CMD_MTDPARTS
91#define CONFIG_MTD_PARTITIONS
Sandeep Paulraj832b9152009-09-08 18:08:06 -040092#define CONFIG_MTD_DEVICE
David Brownell7a846182009-05-15 23:48:37 +020093#define CONFIG_CMD_NAND
94#define CONFIG_CMD_UBI
95#define CONFIG_RBTREE
96#endif
97
David Brownell7a846182009-05-15 23:48:37 +020098#ifdef CONFIG_USB_DAVINCI
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020099#define CONFIG_USB_MUSB_HCD
David Brownell7a846182009-05-15 23:48:37 +0200100#define CONFIG_CMD_USB
101#define CONFIG_USB_STORAGE
102#else
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200103#undef CONFIG_USB_MUSB_HCD
David Brownell7a846182009-05-15 23:48:37 +0200104#undef CONFIG_CMD_USB
105#undef CONFIG_USB_STORAGE
106#endif
107
108#define CONFIG_CRC32_VERIFY
109#define CONFIG_MX_CYCLIC
110
111/* U-Boot general configuration */
David Brownell7a846182009-05-15 23:48:37 +0200112#define CONFIG_BOOTFILE "uImage" /* Boot file name */
113#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
114#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
115#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
116 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_HUSH_PARSER
David Brownell7a846182009-05-15 23:48:37 +0200119#define CONFIG_SYS_LONGHELP
120
Sandeep Paulraj832b9152009-09-08 18:08:06 -0400121#ifdef CONFIG_NAND_DAVINCI
122#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
123#define CONFIG_ENV_IS_IN_NAND
124#define CONFIG_ENV_OFFSET 0x3C0000
125#undef CONFIG_ENV_IS_IN_FLASH
126#endif
David Brownell7a846182009-05-15 23:48:37 +0200127
Sandeep Paulrajee0e6632010-12-18 18:14:49 -0500128#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
129#define CONFIG_CMD_ENV
130#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
131#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
132#define CONFIG_ENV_IS_IN_MMC
133#undef CONFIG_ENV_IS_IN_FLASH
134#endif
135
Sandeep Paulraj832b9152009-09-08 18:08:06 -0400136#define CONFIG_BOOTDELAY 5
David Brownell7a846182009-05-15 23:48:37 +0200137#define CONFIG_BOOTCOMMAND \
138 "dhcp;bootm"
139#define CONFIG_BOOTARGS \
140 "console=ttyS0,115200n8 " \
141 "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
142
143#define CONFIG_CMDLINE_EDITING
144#define CONFIG_VERSION_VARIABLE
145#define CONFIG_TIMESTAMP
146
147#define CONFIG_NET_RETRY_COUNT 10
148
149/* U-Boot memory configuration */
Sandeep Paulraj832b9152009-09-08 18:08:06 -0400150#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
David Brownell7a846182009-05-15 23:48:37 +0200151#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
152#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
153
154/* Linux interfacing */
155#define CONFIG_CMDLINE_TAG
156#define CONFIG_SETUP_MEMORY_TAGS
157#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
158#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
159
160
161/* NAND configuration ... socketed with two chipselects. It normally comes
162 * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
163 * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
164 * pretty much demands the 4-bit ECC support.) You can of course swap in
165 * other parts, including small page ones.
166 *
167 * This presents a single read-only partition for all bootloader stuff.
168 * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
169 * some extra space to help cope with bad blocks in that data. Linux
170 * shouldn't care about its detailed layout, and will probably want to use
171 * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
172 * override this default partitioning using MTDPARTS and cmdlinepart.
173 */
174#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
175
176#ifdef CONFIG_SYS_NAND_LARGEPAGE
177/* Use same layout for 128K/256K blocks; allow some bad blocks */
178#define PART_BOOT "2m(bootloader)ro,"
179#else
180/* Assume 16K erase blocks; allow a few bad ones. */
181#define PART_BOOT "512k(bootloader)ro,"
182#endif
183
184#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
185#define PART_REST "-(filesystem)"
186
187#define MTDPARTS_DEFAULT \
188 "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
189
Sandeep Paulrajbbe597a2010-11-27 18:49:49 -0500190#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
191
192#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
193#define CONFIG_SYS_INIT_SP_ADDR \
194 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
195
David Brownell7a846182009-05-15 23:48:37 +0200196#endif /* __CONFIG_H */