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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Abrahamcf18bff2016-04-23 22:18:08 +05302/*
3 * Exynos7420 pinctrl driver.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahamcf18bff2016-04-23 22:18:08 +05306 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/io.h>
12#include <dm/pinctrl.h>
13#include <dm/root.h>
14#include <fdtdec.h>
15#include <asm/arch/pinmux.h>
16#include "pinctrl-exynos.h"
17
Thomas Abrahamcf18bff2016-04-23 22:18:08 +053018#define GPD1_OFFSET 0xc0
19
20static struct exynos_pinctrl_config_data serial2_conf[] = {
21 {
22 .offset = GPD1_OFFSET + PIN_CON,
23 .mask = 0x00ff0000,
24 .value = 0x00220000,
25 }, {
26 .offset = GPD1_OFFSET + PIN_PUD,
27 .mask = 0x00000f00,
28 .value = 0x00000f00,
29 },
30};
31
32static int exynos7420_pinctrl_request(struct udevice *dev, int peripheral,
33 int flags)
34{
35 struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
36 unsigned long base = priv->base;
37
38 switch (PERIPH_ID_UART2) {
39 case PERIPH_ID_UART2:
40 exynos_pinctrl_setup_peri(serial2_conf,
41 ARRAY_SIZE(serial2_conf), base);
42 break;
43 default:
44 return -ENODEV;
45 }
46
47 return 0;
48}
49
50static struct pinctrl_ops exynos7420_pinctrl_ops = {
51 .set_state = exynos_pinctrl_set_state,
52 .request = exynos7420_pinctrl_request,
53};
54
55/* pin banks of Exynos7420 pin-controller - BUS0 */
56static const struct samsung_pin_bank_data exynos7420_pin_banks0[] = {
57 EXYNOS_PIN_BANK(5, 0x000, "gpb0"),
58 EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
59 EXYNOS_PIN_BANK(2, 0x040, "gpc1"),
60 EXYNOS_PIN_BANK(6, 0x060, "gpc2"),
61 EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
62 EXYNOS_PIN_BANK(4, 0x0a0, "gpd0"),
63 EXYNOS_PIN_BANK(6, 0x0c0, "gpd1"),
64 EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
65 EXYNOS_PIN_BANK(5, 0x100, "gpd4"),
66 EXYNOS_PIN_BANK(4, 0x120, "gpd5"),
67 EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
68 EXYNOS_PIN_BANK(3, 0x160, "gpd7"),
69 EXYNOS_PIN_BANK(2, 0x180, "gpd8"),
70 EXYNOS_PIN_BANK(2, 0x1a0, "gpg0"),
71 EXYNOS_PIN_BANK(4, 0x1c0, "gpg3"),
72};
73
74/* pin banks of Exynos7420 pin-controller - FSYS0 */
75static const struct samsung_pin_bank_data exynos7420_pin_banks1[] = {
76 EXYNOS_PIN_BANK(7, 0x000, "gpr4"),
77};
78
79/* pin banks of Exynos7420 pin-controller - FSYS1 */
80static const struct samsung_pin_bank_data exynos7420_pin_banks2[] = {
81 EXYNOS_PIN_BANK(4, 0x000, "gpr0"),
82 EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
83 EXYNOS_PIN_BANK(5, 0x040, "gpr2"),
84 EXYNOS_PIN_BANK(8, 0x060, "gpr3"),
85};
86
87const struct samsung_pin_ctrl exynos7420_pin_ctrl[] = {
88 {
89 /* pin-controller instance BUS0 data */
90 .pin_banks = exynos7420_pin_banks0,
91 .nr_banks = ARRAY_SIZE(exynos7420_pin_banks0),
92 }, {
93 /* pin-controller instance FSYS0 data */
94 .pin_banks = exynos7420_pin_banks1,
95 .nr_banks = ARRAY_SIZE(exynos7420_pin_banks1),
96 }, {
97 /* pin-controller instance FSYS1 data */
98 .pin_banks = exynos7420_pin_banks2,
99 .nr_banks = ARRAY_SIZE(exynos7420_pin_banks2),
100 },
101};
102
103static const struct udevice_id exynos7420_pinctrl_ids[] = {
104 { .compatible = "samsung,exynos7420-pinctrl",
105 .data = (ulong)exynos7420_pin_ctrl },
106 { }
107};
108
109U_BOOT_DRIVER(pinctrl_exynos7420) = {
110 .name = "pinctrl_exynos7420",
111 .id = UCLASS_PINCTRL,
112 .of_match = exynos7420_pinctrl_ids,
113 .priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
114 .ops = &exynos7420_pinctrl_ops,
115 .probe = exynos_pinctrl_probe,
116 .flags = DM_FLAG_PRE_RELOC
117};