blob: a5a9fd8d7c837f49417a598c0aa6f42d4319ab07 [file] [log] [blame]
Ye Li56499f62021-08-07 16:01:11 +08001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2021 NXP
4 */
5#include <common.h>
6#include <asm/io.h>
7#include <asm/arch/clock.h>
8#include <asm/arch/ddr.h>
9#include <asm/arch/imx-regs.h>
10
11#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR + 4 * 0)
12#define CTL_START 0x1
13
14#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
15#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
16#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
17#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
18#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
19#define DFI_INIT_COMPLETE 0x2
20
21#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
22#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
23
24#define DENALI_PI_00 (DDR_PI_BASE_ADDR + 4 * 0)
25#define PI_START 0x1
26
27#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
28#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
29#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
30#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
31#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
32
33#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624)
34#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537)
35#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
36#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
37
38#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547)
39#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555)
40#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564)
41#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565)
42
43static void ddr_enable_pll_bypass(void)
44{
45 u32 reg_val;
46
47 /* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
48 reg_val = readl(DENALI_PI_04) & ~0x1;
49 writel(reg_val, DENALI_PI_04);
50
51 /* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
52 writel(0x1, DENALI_PI_12);
53
54 /* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
55 reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
56 writel(reg_val, DENALI_PI_11);
57
58 /* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
59 reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
60 writel(reg_val, DENALI_CTL_23);
61
62 /* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
63 reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
64 writel(reg_val, DENALI_PHY_1547);
65
66 /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
67 reg_val = readl(DENALI_PHY_1624) | 0x1;
68 writel(reg_val, DENALI_PHY_1624);
69
70 /* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
71 reg_val = readl(DENALI_PHY_1555) | 0x1;
72 writel(reg_val, DENALI_PHY_1555);
73
74 /* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
75 reg_val = 0x020100;
76 writel(reg_val, DENALI_CTL_25);
77}
78
79int ddr_calibration(unsigned int fsp_table[3])
80{
81 u32 reg_val;
82 u32 int_status_init, phy_freq_req, phy_freq_type;
83 u32 lock_0, lock_1, lock_2;
84 u32 freq_chg_pt, freq_chg_cnt;
85
86 if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
87 ddr_enable_pll_bypass();
88 freq_chg_cnt = 0;
89 freq_chg_pt = 0;
90 } else {
91 reg_val = readl(DENALI_CTL_250);
92 if (((reg_val >> 16) & 0x3) == 1)
93 freq_chg_cnt = 2;
94 else
95 freq_chg_cnt = 3;
96
97 reg_val = readl(DENALI_PI_12);
98 if (reg_val == 0x3) {
99 freq_chg_pt = 1;
100 } else if (reg_val == 0x7) {
101 freq_chg_pt = 2;
102 } else {
103 printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
104 return -1;
105 }
106 }
107
108 /* Assert PI_START parameter and then assert START parameter in Controller. */
109 reg_val = readl(DENALI_PI_00) | PI_START;
110 writel(reg_val, DENALI_PI_00);
111
112 reg_val = readl(DENALI_CTL_00) | CTL_START;
113 writel(reg_val, DENALI_CTL_00);
114
115 /* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
116 do {
117 if (!freq_chg_cnt) {
118 int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
119 /* DDR subsystem is ready for traffic. */
120 if (int_status_init & DFI_INIT_COMPLETE) {
121 debug("complete\n");
122 break;
123 }
124 }
125
126 /*
127 * During leveling, PHY will request for freq change and SoC clock logic
128 * should provide requested frequency
129 * Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1
130 */
131 reg_val = readl(AVD_SIM_LPDDR_CTRL2);
Ye Li7f5dd942021-10-29 09:46:34 +0800132 /* DFS interrupt is set */
133 phy_freq_req = ((reg_val >> 7) & 0x1) && ((reg_val >> 15) & 0x1);
Ye Li56499f62021-08-07 16:01:11 +0800134 if (phy_freq_req) {
135 phy_freq_type = reg_val & 0x1F;
136 if (phy_freq_type == 0x00) {
137 debug("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
138 set_ddr_clk(fsp_table[phy_freq_type] >> 1);
139
140 /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
141 reg_val = readl(AVD_SIM_LPDDR_CTRL2);
142 writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
143 } else if (phy_freq_type == 0x01) {
144 debug("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
145 set_ddr_clk(fsp_table[phy_freq_type] >> 1);
146
147 /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
148 reg_val = readl(AVD_SIM_LPDDR_CTRL2);
149 writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
150 if (freq_chg_pt == 1)
151 freq_chg_cnt--;
152 } else if (phy_freq_type == 0x02) {
153 debug("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
154 set_ddr_clk(fsp_table[phy_freq_type] >> 1);
155
156 /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
157 reg_val = readl(AVD_SIM_LPDDR_CTRL2);
158 writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
159 if (freq_chg_pt == 2)
160 freq_chg_cnt--;
161 }
Ye Li7f5dd942021-10-29 09:46:34 +0800162
163 /* Hardware clear the ack on falling edge of LPDDR_CTRL2:phy_freq_chg_reg */
164 /* Ensure the ack is clear before starting to poll request again */
165 while ((readl(AVD_SIM_LPDDR_CTRL2) & BIT(6)))
166 ;
Ye Li56499f62021-08-07 16:01:11 +0800167 }
168 } while (1);
169
170 /* Check PLL lock status */
171 lock_0 = readl(DENALI_PHY_1564) & 0xffff;
172 lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
173 lock_2 = readl(DENALI_PHY_1565) & 0xffff;
174
175 if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
176 debug("De-Skew PLL failed to lock\n");
177 debug("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
178 return -1;
179 }
180
181 debug("De-Skew PLL is locked and ready\n");
182 return 0;
183}
184
Jacky Bai9cac6e22021-10-29 09:46:33 +0800185static void save_dram_config(struct dram_timing_info2 *timing_info, unsigned long saved_timing_base)
186{
187 int i = 0;
188 struct dram_timing_info2 *saved_timing = (struct dram_timing_info2 *)saved_timing_base;
189 struct dram_cfg_param *cfg;
190
191 saved_timing->ctl_cfg_num = timing_info->ctl_cfg_num;
192 saved_timing->phy_f1_cfg_num = timing_info->phy_f1_cfg_num;
193 saved_timing->phy_f2_cfg_num = timing_info->phy_f2_cfg_num;
194
195 /* save the fsp table */
196 for (i = 0; i < 3; i++)
197 saved_timing->fsp_table[i] = timing_info->fsp_table[i];
198
199 cfg = (struct dram_cfg_param *)(saved_timing_base +
200 sizeof(*timing_info));
201
202 /* save ctl config */
203 saved_timing->ctl_cfg = cfg;
204 for (i = 0; i < timing_info->ctl_cfg_num; i++) {
205 cfg->reg = timing_info->ctl_cfg[i].reg;
206 cfg->val = timing_info->ctl_cfg[i].val;
207 cfg++;
208 }
209
210 /* save phy f1 config */
211 saved_timing->phy_f1_cfg = cfg;
212 for (i = 0; i < timing_info->phy_f1_cfg_num; i++) {
213 cfg->reg = timing_info->phy_f1_cfg[i].reg;
214 cfg->val = timing_info->phy_f1_cfg[i].val;
215 cfg++;
216 }
217
218 /* save phy f2 config */
219 saved_timing->phy_f2_cfg = cfg;
220 for (i = 0; i < timing_info->phy_f2_cfg_num; i++) {
221 cfg->reg = timing_info->phy_f2_cfg[i].reg;
222 cfg->val = timing_info->phy_f2_cfg[i].val;
223 cfg++;
224 }
225}
226
Ye Li56499f62021-08-07 16:01:11 +0800227int ddr_init(struct dram_timing_info2 *dram_timing)
228{
229 int i;
230
231 if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
232 /* Use PLL bypass for boot freq */
233 /* Since PLL can't generate the double freq, Need ddr clock to generate it. */
234 set_ddr_clk(dram_timing->fsp_table[0]); /* Set to boot freq */
235 setbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */
236 } else {
237 set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
238 clrbits_le32(AVD_SIM_BASE_ADDR, 0x1); /* SIM_DDR_CTRL_DIV2_EN */
239 }
240
Jacky Bai9cac6e22021-10-29 09:46:33 +0800241 /* save the dram config into sram for low power mode */
242 save_dram_config(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
243
Ye Li56499f62021-08-07 16:01:11 +0800244 /* Initialize CTL registers */
245 for (i = 0; i < dram_timing->ctl_cfg_num; i++)
246 writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
247
248 /* Initialize PI registers */
249 for (i = 0; i < dram_timing->pi_cfg_num; i++)
250 writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
251
252 /* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
253 writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
254 for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
255 writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
256
257 /* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
258 writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
259 for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
260 writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
261
262 /* Re-enable MULTICAST mode */
263 writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
264
265 return ddr_calibration(dram_timing->fsp_table);
266}