blob: 9aed5dd217af8ae26bf21f3366ea416e56f54743 [file] [log] [blame]
Marek Vasut442c0f12018-08-18 15:58:32 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Designware APB Timer driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <clk.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020012#include <reset.h>
Marek Vasut442c0f12018-08-18 15:58:32 +020013#include <timer.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Marek Vasut442c0f12018-08-18 15:58:32 +020015
16#include <asm/io.h>
17#include <asm/arch/timer.h>
18
19#define DW_APB_LOAD_VAL 0x0
20#define DW_APB_CURR_VAL 0x4
21#define DW_APB_CTRL 0x8
22
Marek Vasut442c0f12018-08-18 15:58:32 +020023struct dw_apb_timer_priv {
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020024 fdt_addr_t regs;
25 struct reset_ctl_bulk resets;
Marek Vasut442c0f12018-08-18 15:58:32 +020026};
27
Sean Anderson947fc2d2020-10-07 14:37:44 -040028static u64 dw_apb_timer_get_count(struct udevice *dev)
Marek Vasut442c0f12018-08-18 15:58:32 +020029{
30 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
31
32 /*
33 * The DW APB counter counts down, but this function
34 * requires the count to be incrementing. Invert the
35 * result.
36 */
Sean Anderson947fc2d2020-10-07 14:37:44 -040037 return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
Marek Vasut442c0f12018-08-18 15:58:32 +020038}
39
40static int dw_apb_timer_probe(struct udevice *dev)
41{
42 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
43 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
44 struct clk clk;
45 int ret;
46
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020047 ret = reset_get_bulk(dev, &priv->resets);
48 if (ret)
49 dev_warn(dev, "Can't get reset: %d\n", ret);
50 else
51 reset_deassert_bulk(&priv->resets);
52
Marek Vasut442c0f12018-08-18 15:58:32 +020053 ret = clk_get_by_index(dev, 0, &clk);
54 if (ret)
55 return ret;
56
57 uc_priv->clock_rate = clk_get_rate(&clk);
58
59 clk_free(&clk);
60
61 /* init timer */
62 writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
63 writel(0xffffffff, priv->regs + DW_APB_CURR_VAL);
64 setbits_le32(priv->regs + DW_APB_CTRL, 0x3);
65
66 return 0;
67}
68
Simon Glassaad29ae2020-12-03 16:55:21 -070069static int dw_apb_timer_of_to_plat(struct udevice *dev)
Marek Vasut442c0f12018-08-18 15:58:32 +020070{
71 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
72
73 priv->regs = dev_read_addr(dev);
74
75 return 0;
76}
77
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +020078static int dw_apb_timer_remove(struct udevice *dev)
79{
80 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
81
82 return reset_release_bulk(&priv->resets);
83}
84
Marek Vasut442c0f12018-08-18 15:58:32 +020085static const struct timer_ops dw_apb_timer_ops = {
86 .get_count = dw_apb_timer_get_count,
87};
88
89static const struct udevice_id dw_apb_timer_ids[] = {
90 { .compatible = "snps,dw-apb-timer" },
91 {}
92};
93
94U_BOOT_DRIVER(dw_apb_timer) = {
95 .name = "dw_apb_timer",
96 .id = UCLASS_TIMER,
97 .ops = &dw_apb_timer_ops,
98 .probe = dw_apb_timer_probe,
Marek Vasut442c0f12018-08-18 15:58:32 +020099 .of_match = dw_apb_timer_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700100 .of_to_plat = dw_apb_timer_of_to_plat,
Simon Goldschmidt0b6b82a2019-10-23 22:23:12 +0200101 .remove = dw_apb_timer_remove,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700102 .priv_auto = sizeof(struct dw_apb_timer_priv),
Marek Vasut442c0f12018-08-18 15:58:32 +0200103};