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git01.mediatek.com / filogic / uboot / 7f135e9ab9cfdb27b55fe5b05019c84ce3efeab0 / . / arch / arm / mach-at91 / include / mach / at91_common.h
blob: f7b411cf7dfa59ca239a373649b43a5f0dd9fc10 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]6 */
7
8#ifndef AT91_COMMON_H
9#define AT91_COMMON_H
10
Daniel Gorsulowski96d1b472009-06-30 23:03:33 +0200[diff] [blame]11void at91_can_hw_init(void);
Bo Shen6f6afad2013-06-26 10:11:06 +0800[diff] [blame]12void at91_gmac_hw_init(void);
Jean-Christophe PLAGNIOL-VILLARDfafa9232009-03-21 21:08:00 +0100[diff] [blame]13void at91_macb_hw_init(void);
Reinhard Meyerc718a562010-08-13 10:31:06 +0200[diff] [blame]14void at91_mci_hw_init(void);
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]15void at91_serial0_hw_init(void);
16void at91_serial1_hw_init(void);
17void at91_serial2_hw_init(void);
Reinhard Meyer6dd03ef2010-11-03 15:38:33 +0100[diff] [blame]18void at91_seriald_hw_init(void);
Jean-Christophe PLAGNIOL-VILLARD12dcdef2009-03-21 21:07:59 +0100[diff] [blame]19void at91_spi0_hw_init(unsigned long cs_mask);
20void at91_spi1_hw_init(unsigned long cs_mask);
Bo Shenf9623df2013-09-11 18:24:51 +0800[diff] [blame]21void at91_udp_hw_init(void);
Jean-Christophe PLAGNIOL-VILLARD4fc81fb2009-03-21 21:08:00 +0100[diff] [blame]22void at91_uhp_hw_init(void);
Wu, Josh3f338c12013-04-16 23:42:44 +0000[diff] [blame]23void at91_lcd_hw_init(void);
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]24void at91_plla_init(u32 pllar);
Heiko Schocherf1e3a8c2014-10-31 08:31:04 +0100[diff] [blame]25void at91_pllb_init(u32 pllar);
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]26void at91_mck_init(u32 mckr);
Wenyou Yang95a50182017-09-13 14:58:49 +0800[diff] [blame]27void at91_mck_init_down(u32 mckr);
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]28void at91_pmc_init(void);
29void mem_init(void);
Heiko Schocher8a84ae12013-11-18 08:07:23 +0100[diff] [blame]30void at91_phy_reset(void);
Heiko Schocherf1e3a8c2014-10-31 08:31:04 +0100[diff] [blame]31void at91_sdram_hw_init(void);
32void at91_mck_init(u32 mckr);
33void at91_spl_board_init(void);
34void at91_disable_wdt(void);
35void matrix_init(void);
Bo Shen0a910282014-12-15 13:24:31 +0800[diff] [blame]36void redirect_int_from_saic_to_aic(void);
Samuel Mescoffc3156fc2016-02-16 09:45:06 +0100[diff] [blame]37void configure_2nd_sram_as_l2_cache(void);
Eugen Hristev5f6ea432019-08-08 07:48:30 +0000[diff] [blame]38#ifdef CONFIG_ATMEL_SFR
39void configure_ddrcfg_input_buffers(bool open);
40#endif
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]41
Wenyou Yanga3b84f42017-09-01 16:26:16 +0800[diff] [blame]42int at91_set_ethaddr(int offset);
Eugen Hristevfedbf302020-08-05 15:30:34 +0300[diff] [blame]43int at91_set_eth1addr(int offset);
Tudor Ambarusd63d7602019-11-13 15:42:54 +0000[diff] [blame]44void at91_spi_nor_set_ethaddr(void);
Wenyou Yang7879f962017-09-13 14:58:47 +0800[diff] [blame]45int at91_video_show_board_info(void);
Wenyou Yanga3b84f42017-09-01 16:26:16 +0800[diff] [blame]46
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +0100[diff] [blame]47#endif /* AT91_COMMON_H */