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git01.mediatek.com / filogic / uboot / 7edb3624a65bb68e0fe6cea6aa821c1239c6ced9 / . / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi
blob: 89e64344c6de1f0f62b169a61fb2302d2456f034 [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
6/ {
7 wdt-reboot {
8 compatible = "wdt-reboot";
9 wdt = <&wdog3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]10 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]11 };
12
13 aliases {
14 usbgadget0 = &usbg1;
15 usbgadget1 = &usbg2;
16 };
17
18 usbg1: usbg1 {
19 compatible = "fsl,imx27-usb-gadget";
20 dr_mode = "peripheral";
21 chipidea,usb = <&usbotg1>;
22 status = "okay";
23 };
24
25 usbg2: usbg2 {
26 compatible = "fsl,imx27-usb-gadget";
27 dr_mode = "peripheral";
28 chipidea,usb = <&usbotg2>;
29 status = "okay";
30 };
31
32 firmware {
33 optee {
34 compatible = "linaro,optee-tz";
35 method = "smc";
36 };
37 };
38};
39
40&{/soc@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
42 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]43};
44
45&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
47 bootph-all;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]48};
49
50&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]52};
53
54&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]56};
57
58&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]60};
61
62&reg_usdhc2_vmmc {
63 u-boot,off-on-delay-us = <20000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]65};
66
67&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]69};
70
71&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]73};
74
75&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]77};
78
79&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]81};
82
83&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]85};
86
87&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]89};
90
91&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]93};
94
95&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]97};
98
99&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]101};
102
103&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]105};
106
107&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]109 fsl,signal-voltage-switch-extra-delay-ms = <8>;
110};
111
112&lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]114};
115
116&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]118};
119
120&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]122};
123
124&pinctrl_lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]126};
127
128&fec {
129 phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
130 phy-reset-duration = <15>;
131 phy-reset-post-delay = <100>;
132};
133
134&eqos {
135 compatible = "fsl,imx-eqos";
136};
137
138&ethphy1 {
139 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
140 reset-assert-us = <15000>;
141 reset-deassert-us = <100000>;
142};
143
144&usbotg1 {
145 status = "okay";
146 extcon = <&ptn5110>;
147};
148
149&usbotg2 {
150 status = "okay";
151 extcon = <&ptn5110_2>;
152};
153
154&s4muap {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]155 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]156 status = "okay";
157};