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git01.mediatek.com / filogic / uboot / 7edb3624a65bb68e0fe6cea6aa821c1239c6ced9 / . / arch / arm / dts / imx8mm-u-boot.dtsi
blob: 7fd5a05fad3c84555535d540acb27db56287b27f [file] [log] [blame]
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]6/ {
7 binman: binman {
8 multiple-images;
9 };
10};
11
Marcel Ziswiler6dd051a2022-11-07 22:22:41 +0100[diff] [blame]12&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-all;
14 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]15};
16
17&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-all;
19 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]20};
21
22&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]24};
25
26&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]28};
29
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]30&binman {
31 u-boot-spl-ddr {
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]32 align = <4>;
33 align-size = <4>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]34 filename = "u-boot-spl-ddr.bin";
35 pad-byte = <0xff>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]36
37 u-boot-spl {
38 align-end = <4>;
Marcel Ziswiler74d5d4f2021-10-23 01:15:15 +0200[diff] [blame]39 filename = "u-boot-spl.bin";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]40 };
41
Peng Fan5db610f42022-07-26 16:41:20 +0800[diff] [blame]42 ddr-1d-imem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]43 filename = "lpddr4_pmu_train_1d_imem.bin";
Peng Fan68811572022-07-26 16:41:22 +0800[diff] [blame]44 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]45 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]46 };
47
Peng Fan5db610f42022-07-26 16:41:20 +0800[diff] [blame]48 ddr-1d-dmem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]49 filename = "lpddr4_pmu_train_1d_dmem.bin";
Peng Fan68811572022-07-26 16:41:22 +0800[diff] [blame]50 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]51 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]52 };
53
Peng Fan5db610f42022-07-26 16:41:20 +0800[diff] [blame]54 ddr-2d-imem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]55 filename = "lpddr4_pmu_train_2d_imem.bin";
Peng Fan68811572022-07-26 16:41:22 +0800[diff] [blame]56 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]57 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]58 };
59
Peng Fan5db610f42022-07-26 16:41:20 +0800[diff] [blame]60 ddr-2d-dmem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]61 filename = "lpddr4_pmu_train_2d_dmem.bin";
Peng Fan68811572022-07-26 16:41:22 +0800[diff] [blame]62 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]63 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]64 };
65 };
66
67 spl {
68 filename = "spl.bin";
69
70 mkimage {
71 args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
72
73 blob {
74 filename = "u-boot-spl-ddr.bin";
75 };
76 };
77 };
78
79 itb {
80 filename = "u-boot.itb";
81
82 fit {
83 description = "Configuration to load ATF before U-Boot";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]84 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
85 fit,fdt-list = "of-list";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]86 #address-cells = <1>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]87
88 images {
89 uboot {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]90 arch = "arm64";
91 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]92 description = "U-Boot (64-bit)";
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]93 load = <CONFIG_TEXT_BASE>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]94 type = "standalone";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]95
Patrick Wildta6ca6912022-01-13 15:22:17 +0100[diff] [blame]96 uboot-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]97 filename = "u-boot-nodtb.bin";
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]98 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]99 };
100 };
101
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]102#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]103 atf {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]104 arch = "arm64";
105 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]106 description = "ARM Trusted Firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]107 entry = <0x920000>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]108 load = <0x920000>;
109 type = "firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]110
Patrick Wildta6ca6912022-01-13 15:22:17 +0100[diff] [blame]111 atf-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]112 filename = "bl31.bin";
Marcel Ziswilerd87d2f12022-04-08 10:06:56 +0200[diff] [blame]113 type = "atf-bl31";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]114 };
115 };
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]116#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]117
118 binman_fip: fip {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]119 arch = "arm64";
120 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]121 description = "Trusted Firmware FIP";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]122 load = <0x40310000>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]123 type = "firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]124 };
125
126 @fdt-SEQ {
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]127 compression = "none";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]128 description = "NAME";
129 type = "flat_dt";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]130
Patrick Wildta6ca6912022-01-13 15:22:17 +0100[diff] [blame]131 uboot-fdt-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]132 filename = "u-boot.dtb";
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]133 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]134 };
135 };
136 };
137
138 configurations {
139 default = "@config-DEFAULT-SEQ";
140
141 binman_configuration: @config-SEQ {
142 description = "NAME";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]143 fdt = "fdt-SEQ";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]144 firmware = "uboot";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]145#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]146 loadables = "atf";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]147#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]148 };
149 };
150 };
151 };
152
153 imx-boot {
154 filename = "flash.bin";
155 pad-byte = <0x00>;
156
Mamta Shuklacd76f3a2022-07-12 14:36:18 +0000[diff] [blame]157#ifdef CONFIG_FSPI_CONF_HEADER
158 fspi_conf_block {
159 filename = CONFIG_FSPI_CONF_FILE;
160 type = "blob-ext";
161 size = <0x1000>;
162 };
163
164 spl {
165 filename = "spl.bin";
166 offset = <0x1000>;
167 type = "blob-ext";
168 };
169
170 binman_uboot: uboot {
171 filename = "u-boot.itb";
172 offset = <0x58C00>;
173 type = "blob-ext";
174 };
175#else
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]176 spl {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]177 filename = "spl.bin";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]178 offset = <0x0>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]179 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]180 };
181
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]182 binman_uboot: uboot {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]183 filename = "u-boot.itb";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200[diff] [blame]184 offset = <0x57c00>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200[diff] [blame]185 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]186 };
Mamta Shuklacd76f3a2022-07-12 14:36:18 +0000[diff] [blame]187#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]188 };
189};
190
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]191&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]192 bootph-all;
193 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]194 /delete-property/ assigned-clocks;
195 /delete-property/ assigned-clock-parents;
196 /delete-property/ assigned-clock-rates;
197};
198
199&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]200 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]201};
202
203&osc_24m {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]204 bootph-all;
205 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]206};
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]207
208&spba1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]209 bootph-all;
210 bootph-pre-ram;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]211};
212
213&spba2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]214 bootph-all;
215 bootph-pre-ram;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]216};