Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2020 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8M_PHANBELL_H |
| 7 | #define __IMX8M_PHANBELL_H |
| 8 | |
| 9 | #include <linux/sizes.h> |
| 10 | #include <asm/arch/imx-regs.h> |
| 11 | |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 12 | #ifdef CONFIG_SPL_BUILD |
| 13 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 14 | |
| 15 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
Tom Rini | fb52b94 | 2022-12-04 10:04:49 -0500 | [diff] [blame] | 16 | #define CFG_MALLOC_F_ADDR 0x182000 |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 17 | /* For RAW image gives a error info not panic */ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 18 | #endif |
| 19 | |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 20 | /* ENET Config */ |
| 21 | /* ENET1 */ |
| 22 | #if defined(CONFIG_CMD_NET) |
Tom Rini | 4e3c8a6 | 2022-12-04 10:03:53 -0500 | [diff] [blame] | 23 | #define CFG_FEC_MXC_PHYADDR 0 |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 24 | #endif |
| 25 | |
Tom Rini | 0c6ed31 | 2022-12-04 10:04:52 -0500 | [diff] [blame] | 26 | #define CFG_MFG_ENV_SETTINGS \ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 27 | "initrd_addr=0x43800000\0" \ |
| 28 | "initrd_high=0xffffffff\0" \ |
| 29 | |
| 30 | /* Initial environment variables */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 31 | #define CFG_EXTRA_ENV_SETTINGS \ |
Tom Rini | 0c6ed31 | 2022-12-04 10:04:52 -0500 | [diff] [blame] | 32 | CFG_MFG_ENV_SETTINGS \ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 33 | "script=boot.scr\0" \ |
| 34 | "image=Image\0" \ |
| 35 | "console=ttymxc0,115200\0" \ |
| 36 | "fdt_addr=0x43000000\0" \ |
| 37 | "fdt_high=0xffffffffffffffff\0" \ |
| 38 | "boot_fdt=try\0" \ |
| 39 | "fdt_file=imx8mq-phanbell.dtb\0" \ |
| 40 | "initrd_addr=0x43800000\0" \ |
| 41 | "initrd_high=0xffffffffffffffff\0" \ |
| 42 | "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ |
Tom Rini | b113bca | 2021-12-11 14:55:52 -0500 | [diff] [blame] | 43 | "mmcpart=1\0" \ |
Peng Fan | bb4bb58 | 2022-04-15 12:23:41 +0800 | [diff] [blame] | 44 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 45 | "mmcautodetect=yes\0" \ |
| 46 | "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ |
| 47 | "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
| 48 | "bootscript=echo Running bootscript from mmc ...; " \ |
| 49 | "source\0" \ |
| 50 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
| 51 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
| 52 | "mmcboot=echo Booting from mmc ...; " \ |
| 53 | "run mmcargs; " \ |
| 54 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| 55 | "if run loadfdt; then " \ |
| 56 | "booti ${loadaddr} - ${fdt_addr}; " \ |
| 57 | "else " \ |
| 58 | "echo WARN: Cannot load the DT; " \ |
| 59 | "fi; " \ |
| 60 | "else " \ |
| 61 | "echo wait for boot; " \ |
| 62 | "fi;\0" \ |
| 63 | "netargs=setenv bootargs console=${console} " \ |
| 64 | "root=/dev/nfs " \ |
| 65 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ |
| 66 | "netboot=echo Booting from net ...; " \ |
| 67 | "run netargs; " \ |
| 68 | "if test ${ip_dyn} = yes; then " \ |
| 69 | "setenv get_cmd dhcp; " \ |
| 70 | "else " \ |
| 71 | "setenv get_cmd tftp; " \ |
| 72 | "fi; " \ |
| 73 | "${get_cmd} ${loadaddr} ${image}; " \ |
| 74 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| 75 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ |
| 76 | "booti ${loadaddr} - ${fdt_addr}; " \ |
| 77 | "else " \ |
| 78 | "echo WARN: Cannot load the DT; " \ |
| 79 | "fi; " \ |
| 80 | "else " \ |
| 81 | "booti; " \ |
| 82 | "fi;\0" |
| 83 | |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 84 | /* Link Definitions */ |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 85 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 86 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 87 | #define CFG_SYS_INIT_RAM_SIZE 0x80000 |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 88 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 89 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 90 | #define PHYS_SDRAM 0x40000000 |
| 91 | #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ |
| 92 | |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 93 | #define CFG_MXC_UART_BASE UART_BASE_ADDR(1) |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 94 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 95 | #define CFG_SYS_FSL_USDHC_NUM 2 |
| 96 | #define CFG_SYS_FSL_ESDHC_ADDR 0 |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 97 | |
Alifer Moraes | a0a2948 | 2020-03-06 07:46:33 -0300 | [diff] [blame] | 98 | #endif |