| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _X86_ARCH_TNC_H_ |
| 7 | #define _X86_ARCH_TNC_H_ |
| 8 | |
| Bin Meng | 239a40a | 2015-10-22 19:13:32 -0700 | [diff] [blame] | 9 | /* IGD Function Disable Register */ |
| 10 | #define IGD_FD 0xc4 |
| 11 | #define FUNC_DISABLE 0x00000001 |
| Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 12 | |
| Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 13 | /* Memory BAR Enable */ |
| 14 | #define MEM_BAR_EN 0x00000001 |
| 15 | |
| 16 | /* LPC PCI Configuration Registers */ |
| 17 | #define LPC_RCBA 0xf0 |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 18 | |
| Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 19 | /* Root Complex Register Block */ |
| 20 | struct tnc_rcba { |
| 21 | u32 rctl; |
| 22 | u32 esd; |
| 23 | u32 rsvd1[2]; |
| 24 | u32 hdd; |
| 25 | u32 rsvd2; |
| 26 | u32 hdba; |
| 27 | u32 rsvd3[3129]; |
| 28 | u32 d31ip; |
| 29 | u32 rsvd4[3]; |
| 30 | u32 d27ip; |
| 31 | u32 rsvd5; |
| 32 | u32 d02ip; |
| 33 | u32 rsvd6; |
| 34 | u32 d26ip; |
| 35 | u32 d25ip; |
| 36 | u32 d24ip; |
| 37 | u32 d23ip; |
| 38 | u32 d03ip; |
| 39 | u32 rsvd7[3]; |
| 40 | u16 d31ir; |
| 41 | u16 rsvd8[3]; |
| 42 | u16 d27ir; |
| 43 | u16 d26ir; |
| 44 | u16 d25ir; |
| 45 | u16 d24ir; |
| 46 | u16 d23ir; |
| 47 | u16 rsvd9[7]; |
| 48 | u16 d02ir; |
| 49 | u16 d03ir; |
| 50 | }; |
| Bin Meng | b8b4440 | 2014-12-17 15:50:44 +0800 | [diff] [blame] | 51 | |
| 52 | #endif /* _X86_ARCH_TNC_H_ */ |