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git01.mediatek.com / filogic / uboot / 7ea43c580c00ba8c85fbdeb4fa4ec340282724f2 / . / arch / riscv / dts / microchip-mpfs.dtsi
blob: 891dd0918b29de118c627fc18294d12a21ebb2a7 [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4#include "dt-bindings/clock/microchip-mpfs-clock.h"
5#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
6#include "dt-bindings/interrupt-controller/riscv-hart.h"
7
8/ {
9 #address-cells = <2>;
10 #size-cells = <2>;
11 model = "Microchip PolarFire SoC";
12 compatible = "microchip,mpfs";
13
14 chosen {
15 };
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 compatible = "sifive,e51", "sifive,rocket0", "riscv";
23 device_type = "cpu";
24 i-cache-block-size = <64>;
25 i-cache-sets = <128>;
26 i-cache-size = <16384>;
27 reg = <0>;
28 riscv,isa = "rv64imac";
29 clocks = <&clkcfg CLK_CPU>;
30 status = "disabled";
31 operating-points = <
32 /* kHz uV */
33 600000 1100000
34 300000 950000
35 150000 750000
36 >;
37 cpu0_intc: interrupt-controller {
38 #interrupt-cells = <1>;
39 compatible = "riscv,cpu-intc";
40 interrupt-controller;
41 };
42 };
43
44 cpu1: cpu@1 {
45 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <32>;
51 device_type = "cpu";
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <32>;
57 mmu-type = "riscv,sv39";
58 reg = <1>;
59 riscv,isa = "rv64imafdc";
60 clocks = <&clkcfg CLK_CPU>;
61 tlb-split;
62 status = "okay";
63 operating-points = <
64 /* kHz uV */
65 600000 1100000
66 300000 950000
67 150000 750000
68 >;
69 cpu1_intc: interrupt-controller {
70 #interrupt-cells = <1>;
71 compatible = "riscv,cpu-intc";
72 interrupt-controller;
73 };
74 };
75
76 cpu2: cpu@2 {
77 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
78 d-cache-block-size = <64>;
79 d-cache-sets = <64>;
80 d-cache-size = <32768>;
81 d-tlb-sets = <1>;
82 d-tlb-size = <32>;
83 device_type = "cpu";
84 i-cache-block-size = <64>;
85 i-cache-sets = <64>;
86 i-cache-size = <32768>;
87 i-tlb-sets = <1>;
88 i-tlb-size = <32>;
89 mmu-type = "riscv,sv39";
90 reg = <2>;
91 riscv,isa = "rv64imafdc";
92 clocks = <&clkcfg CLK_CPU>;
93 tlb-split;
94 status = "okay";
95 operating-points = <
96 /* kHz uV */
97 600000 1100000
98 300000 950000
99 150000 750000
100 >;
101 cpu2_intc: interrupt-controller {
102 #interrupt-cells = <1>;
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 };
106 };
107
108 cpu3: cpu@3 {
109 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
110 d-cache-block-size = <64>;
111 d-cache-sets = <64>;
112 d-cache-size = <32768>;
113 d-tlb-sets = <1>;
114 d-tlb-size = <32>;
115 device_type = "cpu";
116 i-cache-block-size = <64>;
117 i-cache-sets = <64>;
118 i-cache-size = <32768>;
119 i-tlb-sets = <1>;
120 i-tlb-size = <32>;
121 mmu-type = "riscv,sv39";
122 reg = <3>;
123 riscv,isa = "rv64imafdc";
124 clocks = <&clkcfg CLK_CPU>;
125 tlb-split;
126 status = "okay";
127 operating-points = <
128 /* kHz uV */
129 600000 1100000
130 300000 950000
131 150000 750000
132 >;
133 cpu3_intc: interrupt-controller {
134 #interrupt-cells = <1>;
135 compatible = "riscv,cpu-intc";
136 interrupt-controller;
137 };
138 };
139
140 cpu4: cpu@4 {
141 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
142 d-cache-block-size = <64>;
143 d-cache-sets = <64>;
144 d-cache-size = <32768>;
145 d-tlb-sets = <1>;
146 d-tlb-size = <32>;
147 device_type = "cpu";
148 i-cache-block-size = <64>;
149 i-cache-sets = <64>;
150 i-cache-size = <32768>;
151 i-tlb-sets = <1>;
152 i-tlb-size = <32>;
153 mmu-type = "riscv,sv39";
154 reg = <4>;
155 riscv,isa = "rv64imafdc";
156 clocks = <&clkcfg CLK_CPU>;
157 tlb-split;
158 status = "okay";
159 operating-points = <
160 /* kHz uV */
161 600000 1100000
162 300000 950000
163 150000 750000
164 >;
165 cpu4_intc: interrupt-controller {
166 #interrupt-cells = <1>;
167 compatible = "riscv,cpu-intc";
168 interrupt-controller;
169 };
170 };
171 };
172
Conor Dooleye828edd2022-10-25 08:58:49 +0100[diff] [blame]173 refclk: refclk {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 };
177
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]178 soc {
179 #address-cells = <2>;
180 #size-cells = <2>;
181 compatible = "microchip,mpfs-soc", "simple-bus";
182 ranges;
183
184 clint: clint@2000000 {
185 compatible = "sifive,clint0";
186 reg = <0x0 0x2000000 0x0 0xC000>;
187 interrupts-extended =
188 <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
189 &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
190 &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
191 &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
192 &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
193 };
194
195 cachecontroller: cache-controller@2010000 {
196 compatible = "sifive,fu540-c000-ccache", "cache";
197 reg = <0x0 0x2010000 0x0 0x1000>;
198 interrupt-parent = <&plic>;
199 interrupts = <PLIC_INT_L2_METADATA_CORR
200 PLIC_INT_L2_METADATA_UNCORR
201 PLIC_INT_L2_DATA_CORR>;
202 cache-block-size = <64>;
203 cache-level = <2>;
204 cache-sets = <1024>;
205 cache-size = <2097152>;
206 cache-unified;
207 };
208
209 pdma: pdma@3000000 {
210 compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
211 reg = <0x0 0x3000000 0x0 0x8000>;
212 interrupt-parent = <&plic>;
213 interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
214 PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
215 PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
216 PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
217 #dma-cells = <1>;
218 };
219
220 plic: interrupt-controller@c000000 {
221 compatible = "sifive,plic-1.0.0";
222 reg = <0x0 0xc000000 0x0 0x4000000>;
223 #interrupt-cells = <1>;
224 riscv,ndev = <186>;
225 interrupt-controller;
226 interrupts-extended = <&cpu0_intc HART_INT_M_EXT
227 &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
228 &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
229 &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
230 &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
231 };
232
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]233 clkcfg: clkcfg@20002000 {
234 compatible = "microchip,mpfs-clkcfg";
Conor Dooleye828edd2022-10-25 08:58:49 +0100[diff] [blame]235 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]236 reg-names = "mss_sysreg";
237 clocks = <&refclk>;
238 #clock-cells = <1>;
239 clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
240 "mac0", "mac1", "mmc", "timer", /* 4-7 */
241 "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
242 "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
243 "i2c1", "can0", "can1", "usb", /* 16-19 */
244 "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
245 "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
246 "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
247 };
248
249 /* Common node entry for eMMC/SD */
250 mmc: mmc@20008000 {
251 compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
252 reg = <0x0 0x20008000 0x0 0x1000>;
253 clocks = <&clkcfg CLK_MMC>;
254 interrupt-parent = <&plic>;
255 interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
256 max-frequency = <200000000>;
257 status = "disabled";
258 };
259
260 uart0: serial@20000000 {
261 compatible = "ns16550a";
262 reg = <0x0 0x20000000 0x0 0x400>;
263 reg-io-width = <4>;
264 reg-shift = <2>;
265 interrupt-parent = <&plic>;
266 interrupts = <PLIC_INT_MMUART0>;
267 clocks = <&clkcfg CLK_MMUART0>;
268 status = "disabled"; /* Reserved for the HSS */
269 };
270
271 uart1: serial@20100000 {
272 compatible = "ns16550a";
273 reg = <0x0 0x20100000 0x0 0x400>;
274 reg-io-width = <4>;
275 reg-shift = <2>;
276 interrupt-parent = <&plic>;
277 interrupts = <PLIC_INT_MMUART1>;
278 clocks = <&clkcfg CLK_MMUART1>;
279 status = "disabled";
280 };
281
282 uart2: serial@20102000 {
283 compatible = "ns16550a";
284 reg = <0x0 0x20102000 0x0 0x400>;
285 reg-io-width = <4>;
286 reg-shift = <2>;
287 interrupt-parent = <&plic>;
288 interrupts = <PLIC_INT_MMUART2>;
289 clocks = <&clkcfg CLK_MMUART2>;
290 status = "disabled";
291 };
292
293 uart3: serial@20104000 {
294 compatible = "ns16550a";
295 reg = <0x0 0x20104000 0x0 0x400>;
296 reg-io-width = <4>;
297 reg-shift = <2>;
298 interrupt-parent = <&plic>;
299 interrupts = <PLIC_INT_MMUART3>;
300 clocks = <&clkcfg CLK_MMUART3>;
301 status = "disabled";
302 };
303
304 uart4: serial@20106000 {
305 compatible = "ns16550a";
306 reg = <0x0 0x20106000 0x0 0x400>;
307 reg-io-width = <4>;
308 reg-shift = <2>;
309 interrupt-parent = <&plic>;
310 interrupts = <PLIC_INT_MMUART4>;
311 clocks = <&clkcfg CLK_MMUART4>;
312 status = "disabled";
313 };
314
315 spi0: spi@20108000 {
316 compatible = "microchip,mpfs-spi";
317 reg = <0x0 0x20108000 0x0 0x1000>;
318 clocks = <&clkcfg CLK_SPI0>;
319 interrupt-parent = <&plic>;
320 interrupts = <PLIC_INT_SPI0>;
321 num-cs = <8>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
327 spi1: spi@20109000 {
328 compatible = "microchip,mpfs-spi";
329 reg = <0x0 0x20109000 0x0 0x1000>;
330 clocks = <&clkcfg CLK_SPI1>;
331 interrupt-parent = <&plic>;
332 interrupts = <PLIC_INT_SPI1>;
333 num-cs = <8>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 status = "disabled";
337 };
338
339 i2c0: i2c@2010a000 {
340 compatible = "microchip,mpfs-i2c";
341 reg = <0x0 0x2010a000 0x0 0x1000>;
342 clocks = <&clkcfg CLK_I2C0>;
343 interrupt-parent = <&plic>;
344 interrupts = <PLIC_INT_I2C0_MAIN>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
350 i2c1: i2c@2010b000 {
351 compatible = "microchip,mpfs-i2c";
352 reg = <0x0 0x2010b000 0x0 0x1000>;
353 clocks = <&clkcfg CLK_I2C1>;
354 interrupt-parent = <&plic>;
355 interrupts = <PLIC_INT_I2C1_MAIN>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 status = "disabled";
359 };
360
361 can0: can@2010c000 {
362 compatible = "microchip,mpfs-can-uio";
363 reg = <0x0 0x2010c000 0x0 0x1000>;
364 clocks = <&clkcfg CLK_CAN0>;
365 interrupt-parent = <&plic>;
366 interrupts = <PLIC_INT_CAN0>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 status = "disabled";
370 };
371
372 can1: can@2010d000 {
373 compatible = "microchip,mpfs-can-uio";
374 reg = <0x0 0x2010d000 0x0 0x1000>;
375 clocks = <&clkcfg CLK_CAN1>;
376 interrupt-parent = <&plic>;
377 interrupts = <PLIC_INT_CAN1>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 mac0: ethernet@20110000 {
384 compatible = "cdns,macb";
385 reg = <0x0 0x20110000 0x0 0x2000>;
386 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
387 clock-names = "pclk", "hclk";
388 interrupt-parent = <&plic>;
389 interrupts = <PLIC_INT_MAC0_INT
390 PLIC_INT_MAC0_QUEUE1
391 PLIC_INT_MAC0_QUEUE2
392 PLIC_INT_MAC0_QUEUE3
393 PLIC_INT_MAC0_EMAC
394 PLIC_INT_MAC0_MMSL>;
395 local-mac-address = [00 00 00 00 00 00];
396 status = "disabled";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 };
400
401 mac1: ethernet@20112000 {
402 compatible = "cdns,macb";
403 reg = <0x0 0x20112000 0x0 0x2000>;
404 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
405 clock-names = "pclk", "hclk";
406 interrupt-parent = <&plic>;
407 interrupts = <PLIC_INT_MAC1_INT
408 PLIC_INT_MAC1_QUEUE1
409 PLIC_INT_MAC1_QUEUE2
410 PLIC_INT_MAC1_QUEUE3
411 PLIC_INT_MAC1_EMAC
412 PLIC_INT_MAC1_MMSL>;
413 local-mac-address = [00 00 00 00 00 00];
414 status = "disabled";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 };
418
419 gpio0: gpio@20120000 {
420 compatible = "microchip,mpfs-gpio";
421 reg = <0x0 0x20120000 0x0 0x1000>;
422 reg-names = "control";
423 clocks = <&clkcfg CLK_GPIO0>;
424 interrupt-parent = <&plic>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 status = "disabled";
428 };
429
430 gpio1: gpio@20121000 {
431 compatible = "microchip,mpfs-gpio";
432 reg = <000 0x20121000 0x0 0x1000>;
433 reg-names = "control";
434 clocks = <&clkcfg CLK_GPIO1>;
435 interrupt-parent = <&plic>;
436 gpio-controller;
437 #gpio-cells = <2>;
438 status = "disabled";
439 };
440
441 gpio2: gpio@20122000 {
442 compatible = "microchip,mpfs-gpio";
443 reg = <0x0 0x20122000 0x0 0x1000>;
444 reg-names = "control";
445 clocks = <&clkcfg CLK_GPIO2>;
446 interrupt-parent = <&plic>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 status = "disabled";
450 };
451
452 rtc: rtc@20124000 {
453 compatible = "microchip,mpfs-rtc";
454 reg = <0x0 0x20124000 0x0 0x1000>;
455 clocks = <&clkcfg CLK_RTC>;
456 clock-names = "rtc";
457 interrupt-parent = <&plic>;
458 interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 status = "disabled";
462 };
463
464 usb: usb@20201000 {
465 compatible = "microchip,mpfs-usb-host";
466 reg = <0x0 0x20201000 0x0 0x1000>;
467 reg-names = "mc","control";
468 clocks = <&clkcfg CLK_USB>;
469 interrupt-parent = <&plic>;
470 interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
471 interrupt-names = "dma","mc";
472 dr_mode = "host";
473 status = "disabled";
474 };
475
476 qspi: qspi@21000000 {
477 compatible = "microchip,mpfs-qspi";
478 reg = <0x0 0x21000000 0x0 0x1000>;
479 clocks = <&clkcfg CLK_QSPI>;
480 interrupt-parent = <&plic>;
481 interrupts = <PLIC_INT_QSPI>;
482 num-cs = <8>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
487
488 mbox: mailbox@37020000 {
489 compatible = "microchip,mpfs-mailbox";
490 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
491 interrupt-parent = <&plic>;
492 interrupts = <PLIC_INT_G5C_MESSAGE>;
493 #mbox-cells = <1>;
494 status = "disabled";
495 };
496
497 pcie: pcie@2000000000 {
498 compatible = "microchip,pcie-host-1.0";
499 #address-cells = <0x3>;
500 #interrupt-cells = <0x1>;
501 #size-cells = <0x2>;
502 device_type = "pci";
503 reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
504 reg-names = "cfg", "apb";
505 clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
506 clock-names = "fic0", "fic1", "fic3";
507 bus-range = <0x0 0x7f>;
508 interrupt-parent = <&plic>;
509 interrupts = <PLIC_INT_FABRIC_F2H_2>;
510 interrupt-map = <0 0 0 1 &pcie_intc 0>,
511 <0 0 0 2 &pcie_intc 1>,
512 <0 0 0 3 &pcie_intc 2>,
513 <0 0 0 4 &pcie_intc 3>;
514 interrupt-map-mask = <0 0 0 7>;
515 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
516 msi-parent = <&pcie>;
517 msi-controller;
518 mchp,axi-m-atr0 = <0x10 0x0>;
519 status = "disabled";
520 pcie_intc: legacy-interrupt-controller {
521 #address-cells = <0>;
522 #interrupt-cells = <1>;
523 interrupt-controller;
524 };
525 };
526
527 syscontroller: syscontroller {
528 compatible = "microchip,mpfs-sys-controller";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 mboxes = <&mbox 0>;
532 };
533
534 hwrandom: hwrandom {
535 compatible = "microchip,mpfs-rng";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 syscontroller = <&syscontroller>;
539 };
540
541 serialnum: serialnum {
542 compatible = "microchip,mpfs-serial-number";
543 #address-cells = <1>;
544 #size-cells = <1>;
545 syscontroller = <&syscontroller>;
546 };
547
548 fpgadigest: fpgadigest {
549 compatible = "microchip,mpfs-digest";
550 #address-cells = <1>;
551 #size-cells = <1>;
552 syscontroller = <&syscontroller>;
553 };
554
555 devicecert: cert {
556 compatible = "microchip,mpfs-device-cert";
557 #address-cells = <1>;
558 #size-cells = <1>;
559 syscontroller = <&syscontroller>;
560 };
561
562 signature: signature {
563 compatible = "microchip,mpfs-signature";
564 #address-cells = <1>;
565 #size-cells = <1>;
566 syscontroller = <&syscontroller>;
567 };
568 };
569};