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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl024b61c2011-11-01 23:55:01 +00002/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl024b61c2011-11-01 23:55:01 +00007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000015
16/* The first stage boot loader takes care of low level initialization. */
17#define CONFIG_SKIP_LOWLEVEL_INIT
18
19/* Set our official architecture number. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000020#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
21
22/* CPU information */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000023#define CONFIG_ARCH_CPU_INIT
24
25/* ARM asynchronous clock */
26#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
27#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000028
29/* 32kB internal SRAM */
30#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
31#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring72e6d652012-07-13 09:44:01 +000032#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
33 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl024b61c2011-11-01 23:55:01 +000034
35/* 128MB SDRAM in 1 bank */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000036#define CONFIG_SYS_SDRAM_BASE 0x20000000
37#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
38#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
39#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
40#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
41#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
42#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
43 - CONFIG_SYS_MALLOC_LEN)
44
45/* 512kB on-chip NOR flash */
46# define CONFIG_SYS_MAX_FLASH_BANKS 1
47# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
48# define CONFIG_AT91_EFLASH
49# define CONFIG_SYS_MAX_FLASH_SECT 32
50# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
51# define CONFIG_EFLASH_PROTSECTORS 1
52
Tim Schendekehl024b61c2011-11-01 23:55:01 +000053
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +080054/* bootstrap + u-boot + env + linux in dataflash on CS0 */
55#define CONFIG_ENV_OFFSET 0x3DE000
56#define CONFIG_ENV_SIZE (132 << 10)
57#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
58#define CONFIG_ENV_SPI_MAX_HZ 15000000
Tim Schendekehl024b61c2011-11-01 23:55:01 +000059
Tim Schendekehl024b61c2011-11-01 23:55:01 +000060/* NAND flash */
61#ifdef CONFIG_CMD_NAND
62#define CONFIG_SYS_MAX_NAND_DEVICE 1
63#define CONFIG_SYS_NAND_BASE 0x40000000
64#define CONFIG_SYS_NAND_DBW_8
Tim Schendekehl024b61c2011-11-01 23:55:01 +000065/* our ALE is AD21 */
66#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
67/* our CLE is AD22 */
68#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +010069#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl024b61c2011-11-01 23:55:01 +000070#endif
71
72/* JFFS2 */
73#ifdef CONFIG_CMD_JFFS2
Tim Schendekehl024b61c2011-11-01 23:55:01 +000074#define CONFIG_JFFS2_CMDLINE
75#define CONFIG_JFFS2_NAND
76#endif
77
78/* Ethernet */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000079#define CONFIG_NET_RETRY_COUNT 20
80#define CONFIG_MACB
81#define CONFIG_RMII
82#define CONFIG_PHY_ID 0
83#define CONFIG_MACB_SEARCH_PHY
84
85/* MMC */
86#ifdef CONFIG_CMD_MMC
Tim Schendekehl024b61c2011-11-01 23:55:01 +000087#define CONFIG_GENERIC_ATMEL_MCI
88#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
89#endif
90
91/* USB */
92#ifdef CONFIG_CMD_USB
93#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +080094#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl024b61c2011-11-01 23:55:01 +000095#define CONFIG_USB_OHCI_NEW
96#define CONFIG_SYS_USB_OHCI_CPU_INIT
97#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
98#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
99#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000100#endif
101
102/* RTC */
103#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
104#define CONFIG_RTC_PCF8563
105#define CONFIG_SYS_I2C_RTC_ADDR 0x51
106#endif
107
108/* I2C */
109#define CONFIG_SYS_MAX_I2C_BUS 1
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100110
111#define CONFIG_SYS_I2C
112#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
113#define CONFIG_SYS_I2C_SOFT_SPEED 100000
114#define CONFIG_SYS_I2C_SOFT_SLAVE 0
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000115
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000116#define I2C_SOFT_DECLARATIONS
117
118#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
119#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
120
121#define I2C_INIT { \
122 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
123 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
124 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
125 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
126 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
127}
128
129#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
130#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
131#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
132#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
133#define I2C_DELAY udelay(100)
134#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
135
136/* DHCP/BOOTP options */
137#ifdef CONFIG_CMD_DHCP
138#define CONFIG_BOOTP_BOOTFILESIZE
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000139#define CONFIG_SYS_AUTOLOAD "n"
140#endif
141
142/* File systems */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000143
144/* Boot command */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000145#define CONFIG_CMDLINE_TAG
146#define CONFIG_SETUP_MEMORY_TAGS
147#define CONFIG_INITRD_TAG
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +0800148#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
149 "sf read 0x22000000 0xc6000 0x294000; " \
150 "bootm 0x22000000"
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000151
152/* Misc. u-boot settings */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000153
154#endif