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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wang Huanddf89f92014-09-05 13:52:45 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Gaurav Jain119c7002022-06-23 16:31:35 +05304 * Copyright 2019, 2021-2022 NXP
Wang Huanddf89f92014-09-05 13:52:45 +08005 */
6
7#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07008#include <clock_legacy.h>
Simon Glassed38aef2020-05-10 11:40:03 -06009#include <command.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -070010#include <fdt_support.h>
Wang Huanddf89f92014-09-05 13:52:45 +080011#include <i2c.h>
Simon Glassa7b51302019-11-14 12:57:46 -070012#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <net.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Wang Huanddf89f92014-09-05 13:52:45 +080015#include <asm/io.h>
16#include <asm/arch/immap_ls102xa.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/fsl_serdes.h>
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +080019#include <asm/arch/ls102xa_devdis.h>
Yao Yuane0f8f542015-12-05 14:59:10 +080020#include <asm/arch/ls102xa_soc.h>
Yao Yuan064f0a12015-03-03 16:35:18 +080021#include <hwconfig.h>
Wang Huanddf89f92014-09-05 13:52:45 +080022#include <mmc.h>
Mingkai Hu5b0df8a2015-10-26 19:47:41 +080023#include <fsl_csu.h>
Wang Huanddf89f92014-09-05 13:52:45 +080024#include <fsl_ifc.h>
York Sun1006cad2015-04-29 10:35:35 -070025#include <fsl_immap.h>
Wang Huanddf89f92014-09-05 13:52:45 +080026#include <netdev.h>
27#include <fsl_mdio.h>
28#include <tsec.h>
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +080029#include <fsl_devdis.h>
Alison Wang948c6092014-12-03 15:00:48 +080030#include <spl.h>
Simon Glassdbd79542020-05-10 11:40:11 -060031#include <linux/delay.h>
Tang Yuantian8b160bc2015-05-14 17:20:28 +080032#include "../common/sleep.h"
Zhao Qiangf3cc6b72014-09-26 16:25:33 +080033#ifdef CONFIG_U_QE
Qianyu Gongae6a7582016-02-18 13:01:59 +080034#include <fsl_qe.h>
Zhao Qiangf3cc6b72014-09-26 16:25:33 +080035#endif
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +053036#include <fsl_validate.h>
Gaurav Jain119c7002022-06-23 16:31:35 +053037#include <dm/uclass.h>
Wang Huanddf89f92014-09-05 13:52:45 +080038
39DECLARE_GLOBAL_DATA_PTR;
40
41#define VERSION_MASK 0x00FF
42#define BANK_MASK 0x0001
Simon Glass1877f2c2021-03-26 16:13:01 +130043#define CFG_RESET 0x1
Wang Huanddf89f92014-09-05 13:52:45 +080044#define INIT_RESET 0x1
45
46#define CPLD_SET_MUX_SERDES 0x20
47#define CPLD_SET_BOOT_BANK 0x40
48
49#define BOOT_FROM_UPPER_BANK 0x0
50#define BOOT_FROM_LOWER_BANK 0x1
51
52#define LANEB_SATA (0x01)
53#define LANEB_SGMII1 (0x02)
54#define LANEC_SGMII1 (0x04)
55#define LANEC_PCIEX1 (0x08)
56#define LANED_PCIEX2 (0x10)
57#define LANED_SGMII2 (0x20)
58
59#define MASK_LANE_B 0x1
60#define MASK_LANE_C 0x2
61#define MASK_LANE_D 0x4
62#define MASK_SGMII 0x8
63
64#define KEEP_STATUS 0x0
65#define NEED_RESET 0x1
66
Yao Yuan064f0a12015-03-03 16:35:18 +080067#define SOFT_MUX_ON_I2C3_IFC 0x2
68#define SOFT_MUX_ON_CAN3_USB2 0x8
69#define SOFT_MUX_ON_QE_LCD 0x10
70
71#define PIN_I2C3_IFC_MUX_I2C3 0x0
72#define PIN_I2C3_IFC_MUX_IFC 0x1
73#define PIN_CAN3_USB2_MUX_USB2 0x0
74#define PIN_CAN3_USB2_MUX_CAN3 0x1
75#define PIN_QE_LCD_MUX_LCD 0x0
76#define PIN_QE_LCD_MUX_QE 0x1
77
Wang Huanddf89f92014-09-05 13:52:45 +080078struct cpld_data {
79 u8 cpld_ver; /* cpld revision */
80 u8 cpld_ver_sub; /* cpld sub revision */
81 u8 pcba_ver; /* pcb revision number */
82 u8 system_rst; /* reset system by cpld */
83 u8 soft_mux_on; /* CPLD override physical switches Enable */
84 u8 cfg_rcw_src1; /* Reset config word 1 */
85 u8 cfg_rcw_src2; /* Reset config word 2 */
86 u8 vbank; /* Flash bank selection Control */
87 u8 gpio; /* GPIO for TWR-ELEV */
88 u8 i2c3_ifc_mux;
89 u8 mux_spi2;
90 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
91 u8 qe_lcd_mux; /* QE and LCD Selection */
92 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
93 u8 global_rst; /* reset with init CPLD reg to default */
94 u8 rev1; /* Reserved */
95 u8 rev2; /* Reserved */
96};
97
Alison Wangdd45cc52015-10-15 17:54:40 +080098#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Tom Rinie982d182018-01-03 09:01:33 -050099static void cpld_show(void)
Wang Huanddf89f92014-09-05 13:52:45 +0800100{
101 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
102
103 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
104 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
105 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
106 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
107 in_8(&cpld_data->vbank) & BANK_MASK);
108
Tom Rinifad54302022-03-30 18:07:27 -0400109#ifdef DEBUG
Wang Huanddf89f92014-09-05 13:52:45 +0800110 printf("soft_mux_on =%x\n",
111 in_8(&cpld_data->soft_mux_on));
112 printf("cfg_rcw_src1 =%x\n",
113 in_8(&cpld_data->cfg_rcw_src1));
114 printf("cfg_rcw_src2 =%x\n",
115 in_8(&cpld_data->cfg_rcw_src2));
116 printf("vbank =%x\n",
117 in_8(&cpld_data->vbank));
118 printf("gpio =%x\n",
119 in_8(&cpld_data->gpio));
120 printf("i2c3_ifc_mux =%x\n",
121 in_8(&cpld_data->i2c3_ifc_mux));
122 printf("mux_spi2 =%x\n",
123 in_8(&cpld_data->mux_spi2));
124 printf("can3_usb2_mux =%x\n",
125 in_8(&cpld_data->can3_usb2_mux));
126 printf("qe_lcd_mux =%x\n",
127 in_8(&cpld_data->qe_lcd_mux));
128 printf("serdes_mux =%x\n",
129 in_8(&cpld_data->serdes_mux));
130#endif
131}
Alison Wang2145a372014-12-09 17:38:02 +0800132#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800133
134int checkboard(void)
135{
136 puts("Board: LS1021ATWR\n");
Alison Wangdd45cc52015-10-15 17:54:40 +0800137#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanddf89f92014-09-05 13:52:45 +0800138 cpld_show();
Alison Wang2145a372014-12-09 17:38:02 +0800139#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800140
141 return 0;
142}
143
144void ddrmc_init(void)
145{
146 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
Shengzhou Liu80a12ab2016-09-01 14:50:36 +0800147 u32 temp_sdram_cfg, tmp;
Wang Huanddf89f92014-09-05 13:52:45 +0800148
149 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
150
151 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
152 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
153
154 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
155 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
156 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
157 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
158 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
159 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
160
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800161#ifdef CONFIG_DEEP_SLEEP
162 if (is_warm_boot()) {
163 out_be32(&ddr->sdram_cfg_2,
164 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
165 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
166 out_be32(&ddr->init_ext_addr, (1 << 31));
167
168 /* DRAM VRef will not be trained */
169 out_be32(&ddr->ddr_cdr2,
170 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
171 } else
172#endif
173 {
174 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
175 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
176 }
Wang Huanddf89f92014-09-05 13:52:45 +0800177
178 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
179 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
180
181 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
182
183 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
184
185 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
186 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
187
188 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
Wang Huanddf89f92014-09-05 13:52:45 +0800189
190 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
191 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
192
193 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
Shengzhou Liu80a12ab2016-09-01 14:50:36 +0800194
195 /* DDR erratum A-009942 */
196 tmp = in_be32(&ddr->debug[28]);
197 out_be32(&ddr->debug[28], tmp | 0x0070006f);
198
Wang Huanddf89f92014-09-05 13:52:45 +0800199 udelay(1);
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800200
201#ifdef CONFIG_DEEP_SLEEP
202 if (is_warm_boot()) {
203 /* enter self-refresh */
204 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
205 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
206 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
207
208 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
209 } else
210#endif
211 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
212
213 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
214
215#ifdef CONFIG_DEEP_SLEEP
216 if (is_warm_boot()) {
217 /* exit self-refresh */
218 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
219 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
220 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
221 }
222#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800223}
224
225int dram_init(void)
226{
227#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
228 ddrmc_init();
229#endif
230
Alison Wangd6be97b2019-03-06 14:49:14 +0800231 erratum_a008850_post();
232
Wang Huanddf89f92014-09-05 13:52:45 +0800233 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800234
235#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
236 fsl_dp_resume();
237#endif
238
Wang Huanddf89f92014-09-05 13:52:45 +0800239 return 0;
240}
241
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900242int board_eth_init(struct bd_info *bis)
Wang Huanddf89f92014-09-05 13:52:45 +0800243{
Wang Huanddf89f92014-09-05 13:52:45 +0800244 return pci_eth_init(bis);
245}
Wang Huanddf89f92014-09-05 13:52:45 +0800246
Alison Wangdd45cc52015-10-15 17:54:40 +0800247#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Tom Rinie982d182018-01-03 09:01:33 -0500248static void convert_serdes_mux(int type, int need_reset)
249{
250 char current_serdes;
251 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
252
253 current_serdes = cpld_data->serdes_mux;
254
255 switch (type) {
256 case LANEB_SATA:
257 current_serdes &= ~MASK_LANE_B;
258 break;
259 case LANEB_SGMII1:
260 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
261 break;
262 case LANEC_SGMII1:
263 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
264 break;
265 case LANED_SGMII2:
266 current_serdes |= MASK_LANE_D;
267 break;
268 case LANEC_PCIEX1:
269 current_serdes |= MASK_LANE_C;
270 break;
271 case (LANED_PCIEX2 | LANEC_PCIEX1):
272 current_serdes |= MASK_LANE_C;
273 current_serdes &= ~MASK_LANE_D;
274 break;
275 default:
276 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
277 return;
278 }
279
280 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
281 cpld_data->serdes_mux = current_serdes;
282
283 if (need_reset == 1) {
284 printf("Reset board to enable configuration\n");
Simon Glass1877f2c2021-03-26 16:13:01 +1300285 cpld_data->system_rst = CFG_RESET;
Tom Rinie982d182018-01-03 09:01:33 -0500286 }
287}
288
Wang Huanddf89f92014-09-05 13:52:45 +0800289int config_serdes_mux(void)
290{
291 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
292 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
293
294 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
295 switch (protocol) {
296 case 0x10:
297 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
298 convert_serdes_mux(LANED_PCIEX2 |
299 LANEC_PCIEX1, KEEP_STATUS);
300 break;
301 case 0x20:
302 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
303 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
304 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
305 break;
306 case 0x30:
307 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
308 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
309 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
310 break;
311 case 0x70:
312 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
313 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
314 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
315 break;
316 }
317
318 return 0;
319}
Alison Wang2145a372014-12-09 17:38:02 +0800320#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800321
Alison Wangdd45cc52015-10-15 17:54:40 +0800322#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Yao Yuan064f0a12015-03-03 16:35:18 +0800323int config_board_mux(void)
324{
325 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
326 int conflict_flag;
327
328 conflict_flag = 0;
329 if (hwconfig("i2c3")) {
330 conflict_flag++;
331 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
332 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
333 }
334
335 if (hwconfig("ifc")) {
336 conflict_flag++;
337 /* some signals can not enable simultaneous*/
338 if (conflict_flag > 1)
339 goto conflict;
340 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
341 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
342 }
343
344 conflict_flag = 0;
345 if (hwconfig("usb2")) {
346 conflict_flag++;
347 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
348 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
349 }
350
351 if (hwconfig("can3")) {
352 conflict_flag++;
353 /* some signals can not enable simultaneous*/
354 if (conflict_flag > 1)
355 goto conflict;
356 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
357 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
358 }
359
360 conflict_flag = 0;
361 if (hwconfig("lcd")) {
362 conflict_flag++;
363 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
364 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
365 }
366
367 if (hwconfig("qe")) {
368 conflict_flag++;
369 /* some signals can not enable simultaneous*/
370 if (conflict_flag > 1)
371 goto conflict;
372 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
373 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
374 }
375
376 return 0;
377
378conflict:
379 printf("WARNING: pin conflict! MUX setting may failed!\n");
380 return 0;
381}
382#endif
383
Wang Huanddf89f92014-09-05 13:52:45 +0800384int board_early_init_f(void)
385{
386 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
387
388#ifdef CONFIG_TSEC_ENET
Claudiu Manoil51b503e2015-08-12 13:29:14 +0300389 /* clear BD & FR bits for BE BD's and frame data */
390 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
Wang Huanddf89f92014-09-05 13:52:45 +0800391 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
Wang Huanddf89f92014-09-05 13:52:45 +0800392#endif
393
394#ifdef CONFIG_FSL_IFC
395 init_early_memctl_regs();
396#endif
397
Yao Yuane0f8f542015-12-05 14:59:10 +0800398 arch_soc_init();
Alison Wangd42fc522015-01-15 17:29:29 +0800399
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800400#if defined(CONFIG_DEEP_SLEEP)
tang yuantianfcefdad2015-09-24 15:52:02 +0800401 if (is_warm_boot()) {
402 timer_init();
403 dram_init();
404 }
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800405#endif
406
Wang Huanddf89f92014-09-05 13:52:45 +0800407 return 0;
408}
409
Alison Wang948c6092014-12-03 15:00:48 +0800410#ifdef CONFIG_SPL_BUILD
411void board_init_f(ulong dummy)
412{
tang yuantianfcefdad2015-09-24 15:52:02 +0800413 void (*second_uboot)(void);
414
Alison Wang948c6092014-12-03 15:00:48 +0800415 /* Clear the BSS */
416 memset(__bss_start, 0, __bss_end - __bss_start);
417
418 get_clocks();
419
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800420#if defined(CONFIG_DEEP_SLEEP)
421 if (is_warm_boot())
422 fsl_dp_disable_console();
423#endif
424
Alison Wang948c6092014-12-03 15:00:48 +0800425 preloader_console_init();
426
Alison Wang28253032018-10-16 16:19:22 +0800427 timer_init();
Alison Wang948c6092014-12-03 15:00:48 +0800428 dram_init();
429
Alison Wang5dec9d72015-07-09 10:50:07 +0800430 /* Allow OCRAM access permission as R/W */
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800431#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
432 enable_layerscape_ns_access();
Alison Wang5dec9d72015-07-09 10:50:07 +0800433#endif
434
tang yuantianfcefdad2015-09-24 15:52:02 +0800435 /*
436 * if it is woken up from deep sleep, then jump to second
437 * stage uboot and continue executing without recopying
438 * it from SD since it has already been reserved in memeory
439 * in last boot.
440 */
441 if (is_warm_boot()) {
442 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
443 second_uboot();
444 }
445
Alison Wang948c6092014-12-03 15:00:48 +0800446 board_init_r(NULL, 0);
447}
448#endif
449
chenhui zhao08a01d42015-05-15 14:42:30 +0800450#ifdef CONFIG_DEEP_SLEEP
451/* program the regulator (MC34VR500) to support deep sleep */
452void ls1twr_program_regulator(void)
453{
chenhui zhao08a01d42015-05-15 14:42:30 +0800454 u8 i2c_device_id;
455
456#define LS1TWR_I2C_BUS_MC34VR500 1
457#define MC34VR500_ADDR 0x8
458#define MC34VR500_DEVICEID 0x4
459#define MC34VR500_DEVICEID_MASK 0x0f
Igor Opaniukf7c91762021-02-09 13:52:45 +0200460#if CONFIG_IS_ENABLED(DM_I2C)
Biwen Lid15aa9f2019-12-31 15:33:44 +0800461 struct udevice *dev;
462 int ret;
chenhui zhao08a01d42015-05-15 14:42:30 +0800463
Biwen Lid15aa9f2019-12-31 15:33:44 +0800464 ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
465 1, &dev);
466 if (ret) {
467 printf("%s: Cannot find udev for a bus %d\n", __func__,
468 LS1TWR_I2C_BUS_MC34VR500);
469 return;
470 }
471 i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
472 MC34VR500_DEVICEID_MASK;
473 if (i2c_device_id != MC34VR500_DEVICEID) {
474 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
475 return;
476 }
477
478 dm_i2c_reg_write(dev, 0x31, 0x4);
479 dm_i2c_reg_write(dev, 0x4d, 0x4);
480 dm_i2c_reg_write(dev, 0x6d, 0x38);
481 dm_i2c_reg_write(dev, 0x6f, 0x37);
482 dm_i2c_reg_write(dev, 0x71, 0x30);
483#else
484 unsigned int i2c_bus;
chenhui zhao08a01d42015-05-15 14:42:30 +0800485 i2c_bus = i2c_get_bus_num();
486 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
487 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
488 MC34VR500_DEVICEID_MASK;
489 if (i2c_device_id != MC34VR500_DEVICEID) {
490 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
491 return;
492 }
493
494 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
495 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
496 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
497 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
498 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
499
500 i2c_set_bus_num(i2c_bus);
Biwen Lid15aa9f2019-12-31 15:33:44 +0800501#endif
chenhui zhao08a01d42015-05-15 14:42:30 +0800502}
503#endif
504
Wang Huanddf89f92014-09-05 13:52:45 +0800505int board_init(void)
506{
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +0800507#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
508 erratum_a010315();
509#endif
510
Wang Huanddf89f92014-09-05 13:52:45 +0800511#ifndef CONFIG_SYS_FSL_NO_SERDES
512 fsl_serdes_init();
Alison Wangdd45cc52015-10-15 17:54:40 +0800513#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanddf89f92014-09-05 13:52:45 +0800514 config_serdes_mux();
515#endif
Alison Wang2145a372014-12-09 17:38:02 +0800516#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800517
Alison Wang69364922016-02-05 12:48:17 +0800518 ls102xa_smmu_stream_id_init();
Xiubo Li03d40aa2014-11-21 17:40:59 +0800519
Zhao Qiangf3cc6b72014-09-26 16:25:33 +0800520#ifdef CONFIG_U_QE
521 u_qe_init();
522#endif
523
chenhui zhao08a01d42015-05-15 14:42:30 +0800524#ifdef CONFIG_DEEP_SLEEP
525 ls1twr_program_regulator();
526#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800527 return 0;
528}
529
Sumit Garge2ca9432016-06-14 13:52:40 -0400530#if defined(CONFIG_SPL_BUILD)
531void spl_board_init(void)
532{
Gaurav Jain119c7002022-06-23 16:31:35 +0530533 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
534 struct udevice *dev;
535 int ret;
536
537 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
538 if (ret)
539 printf("Failed to initialize caam_jr: %d\n", ret);
540 }
541
Sumit Garge2ca9432016-06-14 13:52:40 -0400542 ls102xa_smmu_stream_id_init();
543}
544#endif
545
tang yuantian9f51db22015-10-16 16:06:05 +0800546#ifdef CONFIG_BOARD_LATE_INIT
547int board_late_init(void)
548{
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +0530549#ifdef CONFIG_CHAIN_OF_TRUST
550 fsl_setenv_chain_of_trust();
551#endif
tang yuantian9f51db22015-10-16 16:06:05 +0800552
553 return 0;
554}
555#endif
556
Ruchika Gupta901ae762014-10-15 11:39:06 +0530557#if defined(CONFIG_MISC_INIT_R)
558int misc_init_r(void)
559{
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +0800560#ifdef CONFIG_FSL_DEVICE_DISABLE
561 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
562#endif
Alison Wangdd45cc52015-10-15 17:54:40 +0800563#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Yao Yuan064f0a12015-03-03 16:35:18 +0800564 config_board_mux();
565#endif
Gaurav Jain476c6392022-03-24 11:50:35 +0530566 return 0;
Ruchika Gupta901ae762014-10-15 11:39:06 +0530567}
568#endif
569
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800570#if defined(CONFIG_DEEP_SLEEP)
571void board_sleep_prepare(void)
572{
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800573#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
574 enable_layerscape_ns_access();
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800575#endif
576}
577#endif
578
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900579int ft_board_setup(void *blob, struct bd_info *bd)
Wang Huanddf89f92014-09-05 13:52:45 +0800580{
581 ft_cpu_setup(blob, bd);
Simon Glass2aec3cc2014-10-23 18:58:47 -0600582
Minghuan Lian0c535242015-03-12 10:58:48 +0800583#ifdef CONFIG_PCI
584 ft_pci_setup(blob, bd);
Minghuan Liana4d6b612014-10-31 13:43:44 +0800585#endif
586
Simon Glass2aec3cc2014-10-23 18:58:47 -0600587 return 0;
Wang Huanddf89f92014-09-05 13:52:45 +0800588}
589
590u8 flash_read8(void *addr)
591{
592 return __raw_readb(addr + 1);
593}
594
595void flash_write16(u16 val, void *addr)
596{
597 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
598
599 __raw_writew(shftval, addr);
600}
601
602u16 flash_read16(void *addr)
603{
604 u16 val = __raw_readw(addr);
605
606 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
607}
608
Tom Rinie982d182018-01-03 09:01:33 -0500609#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
610 && !defined(CONFIG_SPL_BUILD)
Wang Huanddf89f92014-09-05 13:52:45 +0800611static void convert_flash_bank(char bank)
612{
613 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
614
615 printf("Now switch to boot from flash bank %d.\n", bank);
616 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
617 cpld_data->vbank = bank;
618
619 printf("Reset board to enable configuration.\n");
Simon Glass1877f2c2021-03-26 16:13:01 +1300620 cpld_data->system_rst = CFG_RESET;
Wang Huanddf89f92014-09-05 13:52:45 +0800621}
622
Simon Glassed38aef2020-05-10 11:40:03 -0600623static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
624 char *const argv[])
Wang Huanddf89f92014-09-05 13:52:45 +0800625{
626 if (argc != 2)
627 return CMD_RET_USAGE;
628 if (strcmp(argv[1], "0") == 0)
629 convert_flash_bank(BOOT_FROM_UPPER_BANK);
630 else if (strcmp(argv[1], "1") == 0)
631 convert_flash_bank(BOOT_FROM_LOWER_BANK);
632 else
633 return CMD_RET_USAGE;
634
635 return 0;
636}
637
638U_BOOT_CMD(
639 boot_bank, 2, 0, flash_bank_cmd,
640 "Flash bank Selection Control",
641 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
642);
643
Simon Glassed38aef2020-05-10 11:40:03 -0600644static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
645 char *const argv[])
Wang Huanddf89f92014-09-05 13:52:45 +0800646{
647 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
648
649 if (argc > 2)
650 return CMD_RET_USAGE;
651 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
Simon Glass1877f2c2021-03-26 16:13:01 +1300652 cpld_data->system_rst = CFG_RESET;
Wang Huanddf89f92014-09-05 13:52:45 +0800653 else if (strcmp(argv[1], "init") == 0)
654 cpld_data->global_rst = INIT_RESET;
655 else
656 return CMD_RET_USAGE;
657
658 return 0;
659}
660
661U_BOOT_CMD(
662 cpld_reset, 2, 0, cpld_reset_cmd,
663 "Reset via CPLD",
664 "conf\n"
665 " -reset with current CPLD configuration\n"
666 "init\n"
667 " -reset and initial CPLD configuration with default value"
668
669);
670
Tom Rinie982d182018-01-03 09:01:33 -0500671static void print_serdes_mux(void)
Wang Huanddf89f92014-09-05 13:52:45 +0800672{
673 char current_serdes;
674 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
675
676 current_serdes = cpld_data->serdes_mux;
677
678 printf("Serdes Lane B: ");
679 if ((current_serdes & MASK_LANE_B) == 0)
680 printf("SATA,\n");
681 else
682 printf("SGMII 1,\n");
683
684 printf("Serdes Lane C: ");
685 if ((current_serdes & MASK_LANE_C) == 0)
686 printf("SGMII 1,\n");
687 else
688 printf("PCIe,\n");
689
690 printf("Serdes Lane D: ");
691 if ((current_serdes & MASK_LANE_D) == 0)
692 printf("PCIe,\n");
693 else
694 printf("SGMII 2,\n");
695
696 printf("SGMII 1 is on lane ");
697 if ((current_serdes & MASK_SGMII) == 0)
698 printf("C.\n");
699 else
700 printf("B.\n");
701}
702
Simon Glassed38aef2020-05-10 11:40:03 -0600703static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
704 char *const argv[])
Wang Huanddf89f92014-09-05 13:52:45 +0800705{
706 if (argc != 2)
707 return CMD_RET_USAGE;
708 if (strcmp(argv[1], "sata") == 0) {
709 printf("Set serdes lane B to SATA.\n");
710 convert_serdes_mux(LANEB_SATA, NEED_RESET);
711 } else if (strcmp(argv[1], "sgmii1b") == 0) {
712 printf("Set serdes lane B to SGMII 1.\n");
713 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
714 } else if (strcmp(argv[1], "sgmii1c") == 0) {
715 printf("Set serdes lane C to SGMII 1.\n");
716 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
717 } else if (strcmp(argv[1], "sgmii2") == 0) {
718 printf("Set serdes lane D to SGMII 2.\n");
719 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
720 } else if (strcmp(argv[1], "pciex1") == 0) {
721 printf("Set serdes lane C to PCIe X1.\n");
722 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
723 } else if (strcmp(argv[1], "pciex2") == 0) {
724 printf("Set serdes lane C & lane D to PCIe X2.\n");
725 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
726 } else if (strcmp(argv[1], "show") == 0) {
727 print_serdes_mux();
728 } else {
729 return CMD_RET_USAGE;
730 }
731
732 return 0;
733}
734
735U_BOOT_CMD(
736 lane_bank, 2, 0, serdes_mux_cmd,
737 "Multiplexed function setting for SerDes Lanes",
738 "sata\n"
739 " -change lane B to sata\n"
740 "lane_bank sgmii1b\n"
741 " -change lane B to SGMII1\n"
742 "lane_bank sgmii1c\n"
743 " -change lane C to SGMII1\n"
744 "lane_bank sgmii2\n"
745 " -change lane D to SGMII2\n"
746 "lane_bank pciex1\n"
747 " -change lane C to PCIeX1\n"
748 "lane_bank pciex2\n"
749 " -change lane C & lane D to PCIeX2\n"
750 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
751);
Alison Wang2145a372014-12-09 17:38:02 +0800752#endif