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git01.mediatek.com / filogic / uboot / 7e6a4eedae8b957c507bd468ec204cea9746b382 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 37c56181c9cb5702cc1578b1d731ba0b411afe92 [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]27 nvmem1 = &eeprom_ebm;
28 nvmem2 = &eeprom_fmc1;
29 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &dcc;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]38 };
39
40 memory@0 {
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
43 };
44
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]45 si5332_1: si5332_1 { /* u142 - GEM0 */
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 };
50
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]51 ina226-vccint {
52 compatible = "iio-hwmon";
53 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
54 };
55 ina226-vcc-soc {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
58 };
59 ina226-vcc-pmc {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
62 };
63 ina226-vcc-ram {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
66 };
67 ina226-vcc-pslp {
68 compatible = "iio-hwmon";
69 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
70 };
71 ina226-vcc-psfp {
72 compatible = "iio-hwmon";
73 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
74 };
75 ina226-vccaux {
76 compatible = "iio-hwmon";
77 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
78 };
79 ina226-vccaux-pmc {
80 compatible = "iio-hwmon";
81 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
82 };
83 ina226-vcco-500 {
84 compatible = "iio-hwmon";
85 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
86 };
87 ina226-vcco-501 {
88 compatible = "iio-hwmon";
89 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
90 };
91 ina226-vcco-502 {
92 compatible = "iio-hwmon";
93 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
94 };
95 ina226-vcco-503 {
96 compatible = "iio-hwmon";
97 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
98 };
99 ina226-vcc-1v8 {
100 compatible = "iio-hwmon";
101 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
102 };
103 ina226-vcc-3v3 {
104 compatible = "iio-hwmon";
105 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
106 };
107 ina226-vcc-1v2-ddr4 {
108 compatible = "iio-hwmon";
109 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
110 };
111 ina226-vcc-1v1-lp4 {
112 compatible = "iio-hwmon";
113 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
114 };
115 ina226-vadj-fmc {
116 compatible = "iio-hwmon";
117 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
118 };
119 ina226-mgtyavcc {
120 compatible = "iio-hwmon";
121 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
122 };
123 ina226-mgtyavtt {
124 compatible = "iio-hwmon";
125 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
126 };
127 ina226-mgtyvccaux {
128 compatible = "iio-hwmon";
129 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
130 };
131};
132
133&uart0 { /* uart0 MIO38-39 */
134 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]135};
136
137&sdhci1 { /* sd1 MIO45-51 cd in place */
138 status = "okay";
139 no-1-8-v;
140 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]141 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]142};
143
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]144/* GEM SGMII */
145&psgtr {
146 status = "okay";
147 /* gem0 */
148 clocks = <&si5332_1>;
149 clock-names = "ref0";
150};
151
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]152&gem0 {
153 status = "okay";
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]154 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]155 phy-handle = <&phy0>;
156 phy-mode = "sgmii";
157 is-internal-pcspma;
158 phy0: ethernet-phy@0 { /* u131 M88E1512 */
159 reg = <0>;
160 };
161};
162
163&gpio {
164 status = "okay";
165 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
166 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
167 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
168 "", "", "", "", "", /* 15 - 19 */
169 "", "", "", "", "", /* 20 - 24 */
170 "", "", "", "", "", /* 25 - 29 */
171 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
172 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
173 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
174 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
175 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
176 "", "", "", "", "", /* 55 - 59 */
177 "", "", "", "", "", /* 60 - 64 */
178 "", "", "", "", "", /* 65 - 69 */
179 "", "", "", "", "", /* 70 - 74 */
180 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]181 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]182 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
183 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
184 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
185 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]186 "", "", "", "", "", /* 100 - 104 */
187 "", "", "", "", "", /* 105 - 109 */
188 "", "", "", "", "", /* 110 - 114 */
189 "", "", "", "", "", /* 115 - 119 */
190 "", "", "", "", "", /* 120 - 124 */
191 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]192 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]193 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]194 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
195 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]196 "", "", "", "", "", /* 150 - 154 */
197 "", "", "", "", "", /* 155 - 159 */
198 "", "", "", "", "", /* 160 - 164 */
199 "", "", "", "", "", /* 165 - 169 */
200 "", "", "", ""; /* 170 - 174 */
201};
202
203&i2c0 { /* MIO 34-35 - can't stay here */
204 status = "okay";
205 clock-frequency = <400000>;
206 i2c-mux@74 { /* u33 */
207 compatible = "nxp,pca9548";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 reg = <0x74>;
211 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
212 i2c@0 { /* PMBUS */
213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <0>;
216 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]217 /* u179 ir38164 0x19/0x49 vcco_500 */
218 /* u181 ir38164 0x1a/0x4a vcco_501 */
219 /* u183 ir38164 0x1b/0x4b vcco_502 */
220 /* u185 ir38164 0x1e/0x4e vadj_fmc */
221 /* u187 ir38164 0x1F/0x4f mgtyavcc */
222 /* u189 ir38164 0x20/0x50 mgtyavtt */
223 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
224 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]225
226 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
227 compatible = "infineon,irps5401";
228 reg = <0x47>; /* pmbus / i2c 0x17 */
229 };
230 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
231 compatible = "infineon,irps5401";
232 reg = <0x4c>; /* pmbus / i2c 0x1c */
233 };
234 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
235 compatible = "infineon,irps5401";
236 reg = <0x4d>; /* pmbus / i2c 0x1d */
237 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]238 };
239 i2c@1 { /* PMBUS1_INA226 */
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <1>;
243 /* FIXME check alerts coming to SC */
244 vccint: ina226@40 { /* u65 */
245 compatible = "ti,ina226";
246 #io-channel-cells = <1>;
247 label = "ina226-vccint";
248 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]249 shunt-resistor = <500>; /* R440 */
250 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]251 };
252 vcc_soc: ina226@41 { /* u161 */
253 compatible = "ti,ina226";
254 #io-channel-cells = <1>;
255 label = "ina226-vcc-soc";
256 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]257 shunt-resistor = <500>; /* R1702 */
258 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]259 };
260 vcc_pmc: ina226@42 { /* u163 */
261 compatible = "ti,ina226";
262 #io-channel-cells = <1>;
263 label = "ina226-vcc-pmc";
264 reg = <0x42>;
265 shunt-resistor = <5000>; /* R1214 */
266 /* 0.78V @ 500mA */
267 };
268 vcc_ram: ina226@43 { /* u162 */
269 compatible = "ti,ina226";
270 #io-channel-cells = <1>;
271 label = "ina226-vcc-ram";
272 reg = <0x43>;
273 shunt-resistor = <5000>; /* r1221 */
274 /* 0.78V @ 4A */
275 };
276 vcc_pslp: ina226@44 { /* u165 */
277 compatible = "ti,ina226";
278 #io-channel-cells = <1>;
279 label = "ina226-vcc-pslp";
280 reg = <0x44>;
281 shunt-resistor = <5000>; /* R1216 */
282 /* 0.78V @ 1A */
283 };
284 vcc_psfp: ina226@45 { /* u164 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-vcc-psfp";
288 reg = <0x45>;
289 shunt-resistor = <5000>; /* R1219 */
290 /* 0.78V @ 2A */
291 };
292 };
293 i2c@2 { /* PCIE_CLK */
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <2>;
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]297 clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]298 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
299 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]300 reg = <0x6c>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]301 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
302 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
303 };
304 };
305 i2c@3 { /* PMBUS2_INA226 */
306 #address-cells = <1>;
307 #size-cells = <0>;
308 reg = <3>;
309 /* FIXME check alerts coming to SC */
310 vccaux: ina226@40 { /* u166 */
311 compatible = "ti,ina226";
312 #io-channel-cells = <1>;
313 label = "ina226-vccaux";
314 reg = <0x40>;
315 shunt-resistor = <5000>; /* R382 */
316 /* 1.5V @ 3A */
317 };
318 vccaux_pmc: ina226@41 { /* u168 */
319 compatible = "ti,ina226";
320 #io-channel-cells = <1>;
321 label = "ina226-vccaux-pmc";
322 reg = <0x41>;
323 shunt-resistor = <5000>; /* R1246 */
324 /* 1.5V @ 500mA */
325 };
326 vcco_500: ina226@42 { /* u178 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-vcco-500";
330 reg = <0x42>;
331 shunt-resistor = <2000>; /* R1300 */
332 /* 3.3V @ 5A */
333 };
334 vcco_501: ina226@43 { /* u180 */
335 compatible = "ti,ina226";
336 #io-channel-cells = <1>;
337 label = "ina226-vcco-501";
338 reg = <0x43>;
339 shunt-resistor = <2000>; /* R1313 */
340 /* 3.3V @ 5A */
341 };
342 vcco_502: ina226@44 { /* u182 */
343 compatible = "ti,ina226";
344 #io-channel-cells = <1>;
345 label = "ina226-vcco-502";
346 reg = <0x44>;
347 shunt-resistor = <2000>; /* R1330 */
348 /* 3.3V @ 5A */
349 };
350 vcco_503: ina226@45 { /* u172 */
351 compatible = "ti,ina226";
352 #io-channel-cells = <1>;
353 label = "ina226-vcco-503";
354 reg = <0x45>;
355 shunt-resistor = <5000>; /* R1229 */
356 /* 1.8V @ 2A */
357 };
358 vcc_1v8: ina226@46 { /* u173 */
359 compatible = "ti,ina226";
360 #io-channel-cells = <1>;
361 label = "ina226-vcc-1v8";
362 reg = <0x46>;
363 shunt-resistor = <5000>; /* R400 */
364 /* 1.8V @ 6A */
365 };
366 vcc_3v3: ina226@47 { /* u174 */
367 compatible = "ti,ina226";
368 #io-channel-cells = <1>;
369 label = "ina226-vcc-3v3";
370 reg = <0x47>;
371 shunt-resistor = <5000>; /* R1232 */
372 /* 3.3V @ 500mA */
373 };
374 vcc_1v2_ddr4: ina226@48 { /* u176 */
375 compatible = "ti,ina226";
376 #io-channel-cells = <1>;
377 label = "ina226-vcc-1v2-ddr4";
378 reg = <0x48>;
379 shunt-resistor = <5000>; /* R1275 */
380 /* 1.2V @ 4A */
381 };
382 vcc1v1_lp4: ina226@49 { /* u177 */
383 compatible = "ti,ina226";
384 #io-channel-cells = <1>;
385 label = "ina226-vcc1v1-lp4";
386 reg = <0x49>;
387 shunt-resistor = <5000>; /* R1286 */
388 /* 1.1V @ 4A */
389 };
390 vadj_fmc: ina226@4a { /* u184 */
391 compatible = "ti,ina226";
392 #io-channel-cells = <1>;
393 label = "ina226-vadj-fmc";
394 reg = <0x4a>;
395 shunt-resistor = <2000>; /* R1350 */
396 /* 1.5V @ 10A */
397 };
398 mgtyavcc: ina226@4b { /* u186 */
399 compatible = "ti,ina226";
400 #io-channel-cells = <1>;
401 label = "ina226-mgtyavcc";
402 reg = <0x4b>;
403 shunt-resistor = <2000>; /* R1367 */
404 /* 0.88V @ 6A */
405 };
406 mgtyavtt: ina226@4c { /* u188 */
407 compatible = "ti,ina226";
408 #io-channel-cells = <1>;
409 label = "ina226-mgtyavtt";
410 reg = <0x4c>;
411 shunt-resistor = <2000>; /* R1384 */
412 /* 1.2V @ 10A */
413 };
414 mgtyvccaux: ina226@4d { /* u234 */
415 compatible = "ti,ina226";
416 #io-channel-cells = <1>;
417 label = "ina226-mgtyvccaux";
418 reg = <0x4d>;
419 shunt-resistor = <5000>; /* r1679 */
420 /* 1.5V @ 500mA */
421 };
422 };
423 i2c@4 { /* LP_I2C_SM */
424 #address-cells = <1>;
425 #size-cells = <0>;
426 reg = <4>;
427 /* FIXME wires ready but chip is missing */
428 };
429 i2c@5 { /* zSFP_SI570 */
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <5>;
433 si570_zsfp: clock-generator@5d { /* u192 */
434 #clock-cells = <0>;
435 compatible = "silabs,si570";
436 reg = <0x5d>;
437 temperature-stability = <50>;
438 factory-fout = <156250000>;
439 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]440 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]441 };
442 };
443 i2c@6 { /* USER_SI570_1 */
444 #address-cells = <1>;
445 #size-cells = <0>;
446 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]447 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]448 #clock-cells = <0>;
449 compatible = "silabs,si570";
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]450 reg = <0x5d>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]451 temperature-stability = <50>;
452 factory-fout = <100000000>;
453 clock-frequency = <100000000>;
454 clock-output-names = "si570_user1";
455 };
456
457 };
458 i2c@7 { /* USER_SI570_2 */
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <7>;
462 /* FIXME wires ready but chip is missing */
463 };
464 };
465};
466
467&i2c1 { /* i2c1 MIO 36-37 */
468 status = "okay";
469 clock-frequency = <400000>;
470
471 i2c-mux@74 { /* u35 */
472 compatible = "nxp,pca9548";
473 #address-cells = <1>;
474 #size-cells = <0>;
475 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]476 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]477 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
478 dc_i2c: i2c@0 { /* DC_I2C */
479 #address-cells = <1>;
480 #size-cells = <0>;
481 reg = <0>;
482 /* Use for storing information about SC board */
483 eeprom: eeprom@54 { /* u34 - m24128 16kB */
484 compatible = "st,24c128", "atmel,24c128";
485 reg = <0x54>; /* 0x5c too */
486 };
487 si570_ref_clk: clock-generator@5d { /* u32 */
488 #clock-cells = <0>;
489 compatible = "silabs,si570";
490 reg = <0x5d>;
491 temperature-stability = <50>;
492 factory-fout = <33333333>;
493 clock-frequency = <33333333>;
494 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]495 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]496 };
497 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]498 eeprom_ebm: eeprom@52 { /* x-ebm module */
499 compatible = "st,24c128", "atmel,24c128";
500 reg = <0x52>;
501 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]502 };
503 fmc1: i2c@1 { /* FMCP1_IIC */
504 #address-cells = <1>;
505 #size-cells = <0>;
506 reg = <1>;
507 /* FIXME connection to Samtec J51C */
508 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]509 eeprom_fmc1: eeprom@50 {
510 compatible = "st,24c128", "atmel,24c128";
511 reg = <0x50>;
512 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]513 };
514 fmc2: i2c@2 { /* FMCP2_IIC */
515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <2>;
518 /* FIXME connection to Samtec J53C */
519 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]520 eeprom_fmc2: eeprom@50 {
521 compatible = "st,24c128", "atmel,24c128";
522 reg = <0x50>;
523 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]524 };
525 i2c@3 { /* DDR4_DIMM1 */
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <3>;
529 si570_ddr_dimm1: clock-generator@60 { /* u2 */
530 #clock-cells = <0>;
531 compatible = "silabs,si570";
532 reg = <0x60>;
533 temperature-stability = <50>;
534 factory-fout = <200000000>;
535 clock-frequency = <200000000>;
536 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]537 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]538 };
539 };
540 i2c@4 { /* LPDDR4_SI570_CLK2 */
541 #address-cells = <1>;
542 #size-cells = <0>;
543 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]544 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]545 #clock-cells = <0>;
546 compatible = "silabs,si570";
547 reg = <0x60>;
548 temperature-stability = <50>;
549 factory-fout = <200000000>;
550 clock-frequency = <200000000>;
551 clock-output-names = "si570_lpddr4_clk2";
552 };
553 };
554 i2c@5 { /* LPDDR4_SI570_CLK1 */
555 #address-cells = <1>;
556 #size-cells = <0>;
557 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]558 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]559 #clock-cells = <0>;
560 compatible = "silabs,si570";
561 reg = <0x60>;
562 temperature-stability = <50>;
563 factory-fout = <200000000>;
564 clock-frequency = <200000000>;
565 clock-output-names = "si570_lpddr4_clk1";
566 };
567 };
568 i2c@6 { /* HSDP_SI570 */
569 #address-cells = <1>;
570 #size-cells = <0>;
571 reg = <6>;
572 si570_hsdp: clock-generator@5d { /* u5 */
573 #clock-cells = <0>;
574 compatible = "silabs,si570";
575 reg = <0x5d>;
576 temperature-stability = <50>;
577 factory-fout = <156250000>;
578 clock-frequency = <156250000>;
579 clock-output-names = "si570_hsdp_clk";
580 };
581 };
582 i2c@7 { /* 8A34001 - U219B and J310 connector */
583 #address-cells = <1>;
584 #size-cells = <0>;
585 reg = <7>;
586 };
587 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]588 i2c-mux@75 { /* u214 */
589 compatible = "nxp,pca9548";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]593 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]594 i2c@0 { /* SFP0_IIC */
595 #address-cells = <1>;
596 #size-cells = <0>;
597 reg = <0>;
598 /* SFP0 */
599 };
600 i2c@1 { /* SFP1_IIC */
601 #address-cells = <1>;
602 #size-cells = <0>;
603 reg = <1>;
604 /* SFP1 */
605 };
606 i2c@2 { /* QSFP1_I2C */
607 #address-cells = <1>;
608 #size-cells = <0>;
609 reg = <2>;
610 /* QSFP1 */
611 };
612 /* 3 - 7 unused */
613 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]614};
615
616&xilinx_ams {
617 status = "okay";
618};
619
620&ams_ps {
621 status = "okay";
622};
623
624&ams_pl {
625 status = "okay";
626};