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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkc4cbd342005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Meng75574052016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenkc4cbd342005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenkc4cbd342005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenkc4cbd342005-01-09 18:21:42 +000029 * ---
30 */
31
Tom Rini6a5dccc2022-11-16 13:10:41 -050032#define CFG_SYS_CLK 66000000
Tom Rinibb4dd962022-11-16 13:10:37 -050033#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000034
wdenkc4cbd342005-01-09 18:21:42 +000035/* ---
36 * Define baudrate for UART1 (console output, tftp, ...)
37 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Tom Rini6a5dccc2022-11-16 13:10:41 -050038 * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000039 * interface
40 * ---
41 */
42
Tom Rini6a5dccc2022-11-16 13:10:41 -050043#define CFG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000044
45/* ---
wdenkc4cbd342005-01-09 18:21:42 +000046 * Configuration for environment
47 * Environment is embedded in u-boot in the second sector of the flash
48 * ---
49 */
50
angelo@sysam.it6312a952015-03-29 22:54:16 +020051#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060052 . = DEFINED(env_offset) ? env_offset : .; \
53 env/embedded.o(.text);
Jon Loeliger37ec35e2007-07-04 22:31:56 -050054
wdenkc4cbd342005-01-09 18:21:42 +000055/*
56 *-----------------------------------------------------------------------------
57 * Define user parameters that have to be customized most likely
58 *-----------------------------------------------------------------------------
59 */
60
61/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
62
wdenkc4cbd342005-01-09 18:21:42 +000063/* The following settings will be contained in the environment block ; if you
64want to use a neutral environment all those settings can be manually set in
65u-boot: 'set' command */
66
67#if 0
68
wdenkc4cbd342005-01-09 18:21:42 +000069enter a valid image address in flash */
70
wdenkc4cbd342005-01-09 18:21:42 +000071/* User network settings */
72
wdenkc4cbd342005-01-09 18:21:42 +000073#endif
74
wdenkc4cbd342005-01-09 18:21:42 +000075/*---*/
76
wdenkc4cbd342005-01-09 18:21:42 +000077/*
78 *-----------------------------------------------------------------------------
79 * End of user parameters to be customized
80 *-----------------------------------------------------------------------------
81 */
82
83/* ---
84 * Defines memory range for test
85 * ---
86 */
87
wdenkc4cbd342005-01-09 18:21:42 +000088/* ---
89 * Low Level Configuration Settings
90 * (address mappings, register initial values, etc.)
91 * You should know what you are doing if you make changes here.
92 * ---
93 */
94
95/* ---
96 * Base register address
97 * ---
98 */
99
Tom Rini6a5dccc2022-11-16 13:10:41 -0500100#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000101
102/* ---
103 * System Conf. Reg. & System Protection Reg.
104 * ---
105 */
106
Tom Rini6a5dccc2022-11-16 13:10:41 -0500107#define CFG_SYS_SCR 0x0003
108#define CFG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000109
wdenkc4cbd342005-01-09 18:21:42 +0000110/*-----------------------------------------------------------------------
111 * Definitions for initial stack pointer and data area (in internal SRAM)
112 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500113#define CFG_SYS_INIT_RAM_ADDR 0x20000000
114#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
wdenkc4cbd342005-01-09 18:21:42 +0000115
116/*-----------------------------------------------------------------------
117 * Start addresses for the final memory configuration
118 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -0500119 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000120 */
Tom Rinibb4dd962022-11-16 13:10:37 -0500121#define CFG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000122
123/*
124 *-------------------------------------------------------------------------
125 * RAM SIZE (is defined above)
126 *-----------------------------------------------------------------------
127 */
128
Tom Rinibb4dd962022-11-16 13:10:37 -0500129/* #define CFG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000130
131/*
132 *-----------------------------------------------------------------------
133 */
134
Tom Rini6a5dccc2022-11-16 13:10:41 -0500135#define CFG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000136
wdenkc4cbd342005-01-09 18:21:42 +0000137/*
138 * For booting Linux, the board info and command line data
139 * have to be in the first 8 MB of memory, since this is
140 * the maximum mapped by the Linux kernel during initialization ??
141 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500142#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000143
144/*-----------------------------------------------------------------------
wdenkc4cbd342005-01-09 18:21:42 +0000145 * Cache Configuration
146 */
wdenkc4cbd342005-01-09 18:21:42 +0000147
Tom Rini6a5dccc2022-11-16 13:10:41 -0500148#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
149 CFG_SYS_INIT_RAM_SIZE - 8)
150#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
151 CFG_SYS_INIT_RAM_SIZE - 4)
152#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
153#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500154 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600155 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500156#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600157 CF_CACR_DISD | CF_CACR_INVI | \
158 CF_CACR_CEIB | CF_CACR_DCM | \
159 CF_CACR_EUSP)
160
wdenkc4cbd342005-01-09 18:21:42 +0000161/*-----------------------------------------------------------------------
wdenkc4cbd342005-01-09 18:21:42 +0000162 * LED config
163 */
164#define LED_STAT_0 0xffff /*all LEDs off*/
165#define LED_STAT_1 0xfffe
166#define LED_STAT_2 0xfffd
167#define LED_STAT_3 0xfffb
168#define LED_STAT_4 0xfff7
169#define LED_STAT_5 0xffef
170#define LED_STAT_6 0xffdf
171#define LED_STAT_7 0xff00 /*all LEDs on*/
172
173/*-----------------------------------------------------------------------
174 * Port configuration (GPIO)
175 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500176#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000177GPIO*/
Tom Rini6a5dccc2022-11-16 13:10:41 -0500178#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000179(1^=output, 0^=input) */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500180#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
181#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000182configuration */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500183#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
184#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
185#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000186
187#endif /* _CONFIG_COBRA5272_H */