blob: 161cf37dc48ac569fe6eafa85799a184147039af [file] [log] [blame]
Alexey Brodkin23d1b352015-02-24 17:08:44 +03001/*
2 * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <linux/linkage.h>
8
9/*
10 * Note on the LD/ST addressing modes with address register write-back
11 *
12 * LD.a same as LD.aw
13 *
14 * LD.a reg1, [reg2, x] => Pre Incr
15 * Eff Addr for load = [reg2 + x]
16 *
17 * LD.ab reg1, [reg2, x] => Post Incr
18 * Eff Addr for load = [reg2]
19 */
20
21.macro PUSH reg
22 st.a \reg, [%sp, -4]
23.endm
24
25.macro PUSHAX aux
26 lr %r9, [\aux]
27 PUSH %r9
28.endm
29
30.macro SAVE_R1_TO_R24
31 PUSH %r1
32 PUSH %r2
33 PUSH %r3
34 PUSH %r4
35 PUSH %r5
36 PUSH %r6
37 PUSH %r7
38 PUSH %r8
39 PUSH %r9
40 PUSH %r10
41 PUSH %r11
42 PUSH %r12
43 PUSH %r13
44 PUSH %r14
45 PUSH %r15
46 PUSH %r16
47 PUSH %r17
48 PUSH %r18
49 PUSH %r19
50 PUSH %r20
51 PUSH %r21
52 PUSH %r22
53 PUSH %r23
54 PUSH %r24
55.endm
56
57.macro SAVE_ALL_SYS
58 /* saving %r0 to reg->r0 in advance since we read %ecr into it */
59 st %r0, [%sp, -8]
60 lr %r0, [%ecr] /* all stack addressing is manual so far */
61 st %r0, [%sp]
62 st %sp, [%sp, -4]
63 /* now move %sp to reg->r0 position so we can do "push" automatically */
64 sub %sp, %sp, 8
65
66 SAVE_R1_TO_R24
67 PUSH %r25
68 PUSH %gp
69 PUSH %fp
70 PUSH %blink
71 PUSHAX %eret
72 PUSHAX %erstatus
73 PUSH %lp_count
74 PUSHAX %lp_end
75 PUSHAX %lp_start
76 PUSHAX %erbta
77.endm
78
79.macro SAVE_EXCEPTION_SOURCE
80#ifdef CONFIG_MMU
81 /* If MMU exists exception faulting address is loaded in EFA reg */
82 lr %r0, [%efa]
83#else
84 /* Otherwise in ERET (exception return) reg */
85 lr %r0, [%eret]
86#endif
87.endm
88
89ENTRY(memory_error)
90 SAVE_ALL_SYS
91 SAVE_EXCEPTION_SOURCE
92 mov %r1, %sp
93 j do_memory_error
94ENDPROC(memory_error)
95
96ENTRY(instruction_error)
97 SAVE_ALL_SYS
98 SAVE_EXCEPTION_SOURCE
99 mov %r1, %sp
100 j do_instruction_error
101ENDPROC(instruction_error)
102
103ENTRY(interrupt_handler)
104 /* Todo - save and restore CPU context when interrupts will be in use */
105 bl do_interrupt_handler
106 rtie
107ENDPROC(interrupt_handler)
108
109ENTRY(EV_MachineCheck)
110 SAVE_ALL_SYS
111 SAVE_EXCEPTION_SOURCE
112 mov %r1, %sp
113 j do_machine_check_fault
114ENDPROC(EV_MachineCheck)
115
116ENTRY(EV_TLBMissI)
117 SAVE_ALL_SYS
118 mov %r0, %sp
119 j do_itlb_miss
120ENDPROC(EV_TLBMissI)
121
122ENTRY(EV_TLBMissD)
123 SAVE_ALL_SYS
124 mov %r0, %sp
125 j do_dtlb_miss
126ENDPROC(EV_TLBMissD)
127
128ENTRY(EV_TLBProtV)
129 SAVE_ALL_SYS
130 SAVE_EXCEPTION_SOURCE
131 mov %r1, %sp
132 j do_tlb_prot_violation
133ENDPROC(EV_TLBProtV)
134
135ENTRY(EV_PrivilegeV)
136 SAVE_ALL_SYS
137 mov %r0, %sp
138 j do_privilege_violation
139ENDPROC(EV_PrivilegeV)
140
141ENTRY(EV_Trap)
142 SAVE_ALL_SYS
143 mov %r0, %sp
144 j do_trap
145ENDPROC(EV_Trap)
146
147ENTRY(EV_Extension)
148 SAVE_ALL_SYS
149 mov %r0, %sp
150 j do_extension
151ENDPROC(EV_Extension)