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git01.mediatek.com / filogic / uboot / 7e0673d77b9bc96e1334b0a82655c38514736c86 / . / configs / mk808_defconfig
blob: 5a264eb9e17271d65abd1cf7b238e5f6319e5f57 [file] [log] [blame]
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
3CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
4CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
5# CONFIG_SPL_SYS_THUMB_BUILD is not set
6# CONFIG_TPL_SYS_THUMB_BUILD is not set
7# CONFIG_SPL_USE_ARCH_MEMCPY is not set
8# CONFIG_SPL_USE_ARCH_MEMSET is not set
9CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]10CONFIG_TEXT_BASE=0x60408000
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]11CONFIG_SYS_MALLOC_F_LEN=0x2000
12CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]13CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
14CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]15CONFIG_ENV_SIZE=0x8000
16CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
17CONFIG_SPL_TEXT_BASE=0x60000000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]18CONFIG_DM_RESET=y
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]19CONFIG_ROCKCHIP_RK3066=y
20# CONFIG_ROCKCHIP_STIMER is not set
Johan Jonker7e0673d2023-03-19 16:06:11 +0100[diff] [blame^]21CONFIG_TPL_TEXT_BASE=0x10080c00
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]22CONFIG_TPL_STACK=0x1008FFFF
23CONFIG_TARGET_MK808=y
24CONFIG_SPL_STACK_R_ADDR=0x70000000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]25CONFIG_SPL_STACK=0x1008ffff
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]26CONFIG_DEBUG_UART_BASE=0x20064000
27CONFIG_DEBUG_UART_CLOCK=24000000
28CONFIG_SPL_FS_FAT=y
29CONFIG_SYS_LOAD_ADDR=0x70800800
Tom Rinie0a54502022-07-25 17:19:18 -0400[diff] [blame]30CONFIG_TPL_MAX_SIZE=0x7ffc
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]31CONFIG_SPL_PAYLOAD="u-boot.bin"
32CONFIG_DEBUG_UART=y
33CONFIG_SD_BOOT=y
34CONFIG_USE_PREBOOT=y
35CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb"
36# CONFIG_DISPLAY_CPUINFO is not set
37CONFIG_DISPLAY_BOARDINFO_LATE=y
38CONFIG_BOARD_LATE_INIT=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]39CONFIG_SPL_MAX_SIZE=0x32000
40CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]41CONFIG_SPL_NO_BSS_LIMIT=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]42# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]43CONFIG_SPL_STACK_R=y
44CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
45CONFIG_SPL_SEPARATE_BSS=y
46CONFIG_SPL_FS_EXT4=y
47CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
48CONFIG_TPL_NEEDS_SEPARATE_STACK=y
Tom Riniae17fa32022-05-11 18:01:06 -0400[diff] [blame]49CONFIG_SYS_CBSIZE=256
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]50CONFIG_SYS_PBSIZE=276
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]51# CONFIG_BOOTM_PLAN9 is not set
52# CONFIG_BOOTM_RTEMS is not set
53# CONFIG_BOOTM_VXWORKS is not set
54CONFIG_CMD_GPT=y
55CONFIG_CMD_MMC=y
56# CONFIG_CMD_SETEXPR is not set
57CONFIG_CMD_CACHE=y
58CONFIG_CMD_TIME=y
59CONFIG_CMD_REGULATOR=y
60CONFIG_SPL_OF_CONTROL=y
61CONFIG_TPL_OF_CONTROL=y
62CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
63CONFIG_OF_DTB_PROPS_REMOVE=y
64CONFIG_SPL_OF_PLATDATA=y
65CONFIG_TPL_OF_PLATDATA=y
66CONFIG_SYS_RELOC_GD_ENV_ADDR=y
67# CONFIG_NET is not set
68CONFIG_TPL_DM=y
69# CONFIG_DM_WARN is not set
70CONFIG_REGMAP=y
71CONFIG_SPL_REGMAP=y
72CONFIG_TPL_REGMAP=y
73CONFIG_SYSCON=y
74CONFIG_SPL_SYSCON=y
75CONFIG_TPL_SYSCON=y
76# CONFIG_SIMPLE_BUS is not set
77# CONFIG_SPL_SIMPLE_BUS is not set
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]78CONFIG_CLK=y
79CONFIG_SPL_CLK=y
80CONFIG_TPL_CLK=y
81CONFIG_ROCKCHIP_GPIO=y
82# CONFIG_SPL_DM_I2C is not set
83CONFIG_LED=y
84CONFIG_LED_GPIO=y
85CONFIG_MMC_IO_VOLTAGE=y
86CONFIG_SPL_MMC_IO_VOLTAGE=y
87CONFIG_MMC_UHS_SUPPORT=y
88CONFIG_SPL_MMC_UHS_SUPPORT=y
89CONFIG_MMC_DW=y
90CONFIG_MMC_DW_ROCKCHIP=y
91CONFIG_SF_DEFAULT_SPEED=20000000
92CONFIG_PINCTRL=y
93CONFIG_DM_PMIC=y
94# CONFIG_SPL_PMIC_CHILDREN is not set
95CONFIG_DM_REGULATOR_FIXED=y
96CONFIG_DM_REGULATOR_GPIO=y
97CONFIG_RAM=y
98CONFIG_SPL_RAM=y
99CONFIG_TPL_RAM=y
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]100# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
101CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]102CONFIG_SYS_NS16550_MEM32=y
Johan Jonker11b16f92022-04-16 17:09:49 +0200[diff] [blame]103CONFIG_ROCKCHIP_SERIAL=y
104CONFIG_SYSRESET=y
105CONFIG_TIMER=y
106CONFIG_SPL_TIMER=y
107CONFIG_TPL_TIMER=y
108CONFIG_DESIGNWARE_APB_TIMER=y
109CONFIG_SPL_TINY_MEMSET=y
110CONFIG_ERRNO_STR=y
111# CONFIG_TPL_OF_LIBFDT is not set