| Peng Fan | 0c830d3 | 2018-10-18 14:28:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2018 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef SC_PM_API_H |
| 7 | #define SC_PM_API_H |
| 8 | |
| 9 | /* Defines for sc_pm_power_mode_t */ |
| 10 | #define SC_PM_PW_MODE_OFF 0U /* Power off */ |
| 11 | #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ |
| 12 | #define SC_PM_PW_MODE_LP 2U /* Power in low-power */ |
| 13 | #define SC_PM_PW_MODE_ON 3U /* Power on */ |
| 14 | |
| 15 | /* Defines for sc_pm_clk_t */ |
| 16 | #define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ |
| 17 | #define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ |
| 18 | #define SC_PM_CLK_PER 2U /* Peripheral clock */ |
| 19 | #define SC_PM_CLK_PHY 3U /* Phy clock */ |
| 20 | #define SC_PM_CLK_MISC 4U /* Misc clock */ |
| 21 | #define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ |
| 22 | #define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ |
| 23 | #define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ |
| 24 | #define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ |
| 25 | #define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ |
| 26 | #define SC_PM_CLK_CPU 2U /* CPU clock */ |
| 27 | #define SC_PM_CLK_PLL 4U /* PLL */ |
| 28 | #define SC_PM_CLK_BYPASS 4U /* Bypass clock */ |
| 29 | |
| 30 | /* Defines for sc_pm_clk_mode_t */ |
| 31 | #define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ |
| 32 | #define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ |
| 33 | #define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ |
| 34 | #define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ |
| 35 | #define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ |
| 36 | #define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ |
| 37 | |
| 38 | typedef u8 sc_pm_power_mode_t; |
| 39 | typedef u8 sc_pm_clk_t; |
| 40 | typedef u8 sc_pm_clk_mode_t; |
| 41 | typedef u8 sc_pm_clk_parent_t; |
| 42 | typedef u32 sc_pm_clock_rate_t; |
| 43 | |
| 44 | #endif /* SC_PM_API_H */ |