blob: 5a4f8358c9f522b1c871a722211b63603939867d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Faneae4de22018-01-10 13:20:37 +08002/*
Gaurav Jain81113a02022-03-24 11:50:27 +05303 * Copyright 2017-2019, 2021 NXP
Peng Faneae4de22018-01-10 13:20:37 +08004 *
5 * Peng Fan <peng.fan@nxp.com>
Peng Faneae4de22018-01-10 13:20:37 +08006 */
7
8#include <common.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07009#include <cpu_func.h>
Simon Glassfc557362022-03-04 08:43:05 -070010#include <event.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Peng Faneae4de22018-01-10 13:20:37 +080013#include <asm/arch/imx-regs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Peng Faneae4de22018-01-10 13:20:37 +080015#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/mach-imx/hab.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/syscounter.h>
Peng Fana35215d2020-07-09 13:39:26 +080021#include <asm/ptrace.h>
Peng Faneae4de22018-01-10 13:20:37 +080022#include <asm/armv8/mmu.h>
Peng Fanc98e0322019-08-27 06:25:58 +000023#include <dm/uclass.h>
Gaurav Jain81113a02022-03-24 11:50:27 +053024#include <dm/device.h>
Peng Fana35215d2020-07-09 13:39:26 +080025#include <efi_loader.h>
Ye Li0513f362019-07-15 01:16:46 -070026#include <env.h>
27#include <env_internal.h>
Peng Faneae4de22018-01-10 13:20:37 +080028#include <errno.h>
29#include <fdt_support.h>
30#include <fsl_wdog.h>
31#include <imx_sip.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060032#include <linux/bitops.h>
Peng Faneae4de22018-01-10 13:20:37 +080033
34DECLARE_GLOBAL_DATA_PTR;
35
Stefano Babicf8b509b2019-09-20 08:47:53 +020036#if defined(CONFIG_IMX_HAB)
Peng Faneae4de22018-01-10 13:20:37 +080037struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
38 .bank = 1,
39 .word = 3,
40};
41#endif
42
43int timer_init(void)
44{
45#ifdef CONFIG_SPL_BUILD
46 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
47 unsigned long freq = readl(&sctr->cntfid0);
48
49 /* Update with accurate clock frequency */
50 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
51
52 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
53 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
54#endif
55
56 gd->arch.tbl = 0;
57 gd->arch.tbu = 0;
58
59 return 0;
60}
61
62void enable_tzc380(void)
63{
64 struct iomuxc_gpr_base_regs *gpr =
65 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
66
67 /* Enable TZASC and lock setting */
68 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
69 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010070
71 /*
72 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
73 * order to avoid AXI Bus errors when GPU is in use
74 */
Peng Fanda7a16c2022-04-29 16:18:49 +080075 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010076
77 /*
78 * imx8mn and imx8mp implements the lock bit for
79 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
80 */
Peng Fanda7a16c2022-04-29 16:18:49 +080081 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010082
Ye Li4c97c462019-08-27 06:25:34 +000083 /*
84 * set Region 0 attribute to allow secure and non-secure
85 * read/write permission. Found some masters like usb dwc3
86 * controllers can't work with secure memory.
87 */
88 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
Peng Faneae4de22018-01-10 13:20:37 +080089}
90
91void set_wdog_reset(struct wdog_regs *wdog)
92{
93 /*
94 * Output WDOG_B signal to reset external pmic or POR_B decided by
95 * the board design. Without external reset, the peripherals/DDR/
96 * PMIC are not reset, that may cause system working abnormal.
97 * WDZST bit is write-once only bit. Align this bit in kernel,
98 * otherwise kernel code will have no chance to set this bit.
99 */
100 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
101}
102
Marek Vasut003969b2022-12-22 01:46:40 +0100103#ifdef CONFIG_ARMV8_PSCI
104#define PTE_MAP_NS PTE_BLOCK_NS
105#else
106#define PTE_MAP_NS 0
107#endif
108
Peng Faneae4de22018-01-10 13:20:37 +0800109static struct mm_region imx8m_mem_map[] = {
110 {
111 /* ROM */
112 .virt = 0x0UL,
113 .phys = 0x0UL,
114 .size = 0x100000UL,
115 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
116 PTE_BLOCK_OUTER_SHARE
117 }, {
Gary Bisson5c72a452018-11-14 17:55:28 +0100118 /* CAAM */
119 .virt = 0x100000UL,
120 .phys = 0x100000UL,
121 .size = 0x8000UL,
122 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
123 PTE_BLOCK_NON_SHARE |
124 PTE_BLOCK_PXN | PTE_BLOCK_UXN
125 }, {
Marek Vasutb1738e02021-02-25 21:52:26 +0100126 /* OCRAM_S */
127 .virt = 0x180000UL,
128 .phys = 0x180000UL,
129 .size = 0x8000UL,
130 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100131 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Marek Vasutb1738e02021-02-25 21:52:26 +0100132 }, {
Gary Bisson5c72a452018-11-14 17:55:28 +0100133 /* TCM */
134 .virt = 0x7C0000UL,
135 .phys = 0x7C0000UL,
136 .size = 0x80000UL,
137 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
138 PTE_BLOCK_NON_SHARE |
Marek Vasut003969b2022-12-22 01:46:40 +0100139 PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
Gary Bisson5c72a452018-11-14 17:55:28 +0100140 }, {
Peng Faneae4de22018-01-10 13:20:37 +0800141 /* OCRAM */
142 .virt = 0x900000UL,
143 .phys = 0x900000UL,
144 .size = 0x200000UL,
145 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100146 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Faneae4de22018-01-10 13:20:37 +0800147 }, {
148 /* AIPS */
149 .virt = 0xB00000UL,
150 .phys = 0xB00000UL,
151 .size = 0x3f500000UL,
152 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
153 PTE_BLOCK_NON_SHARE |
154 PTE_BLOCK_PXN | PTE_BLOCK_UXN
155 }, {
156 /* DRAM1 */
157 .virt = 0x40000000UL,
158 .phys = 0x40000000UL,
Peng Fanb749b5e2019-08-27 06:25:27 +0000159 .size = PHYS_SDRAM_SIZE,
Peng Faneae4de22018-01-10 13:20:37 +0800160 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100161 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Fanb749b5e2019-08-27 06:25:27 +0000162#ifdef PHYS_SDRAM_2_SIZE
Peng Faneae4de22018-01-10 13:20:37 +0800163 }, {
164 /* DRAM2 */
165 .virt = 0x100000000UL,
166 .phys = 0x100000000UL,
Peng Fanb749b5e2019-08-27 06:25:27 +0000167 .size = PHYS_SDRAM_2_SIZE,
Peng Faneae4de22018-01-10 13:20:37 +0800168 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100169 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Fanb749b5e2019-08-27 06:25:27 +0000170#endif
Peng Faneae4de22018-01-10 13:20:37 +0800171 }, {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800172 /* empty entrie to split table entry 5 if needed when TEEs are used */
173 0,
174 }, {
Peng Faneae4de22018-01-10 13:20:37 +0800175 /* List terminator */
176 0,
177 }
178};
179
180struct mm_region *mem_map = imx8m_mem_map;
181
Marek Vasute48aac02021-02-27 14:59:00 +0100182static unsigned int imx8m_find_dram_entry_in_mem_map(void)
183{
184 int i;
185
186 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
Tom Rinibb4dd962022-11-16 13:10:37 -0500187 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
Marek Vasute48aac02021-02-27 14:59:00 +0100188 return i;
189
190 hang(); /* Entry not found, this must never happen. */
191}
192
Peng Fanb749b5e2019-08-27 06:25:27 +0000193void enable_caches(void)
194{
Ye Li453bfcb2022-04-07 15:55:56 +0800195 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
196 * If OPTEE does not run, still update the MMU table according to dram banks structure
197 * to set correct dram size from board_phys_sdram_size
198 */
199 int i = 0;
200 /*
201 * please make sure that entry initial value matches
202 * imx8m_mem_map for DRAM1
203 */
204 int entry = imx8m_find_dram_entry_in_mem_map();
205 u64 attrs = imx8m_mem_map[entry].attrs;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800206
Ye Li453bfcb2022-04-07 15:55:56 +0800207 while (i < CONFIG_NR_DRAM_BANKS &&
208 entry < ARRAY_SIZE(imx8m_mem_map)) {
209 if (gd->bd->bi_dram[i].start == 0)
210 break;
211 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
212 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
213 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
214 imx8m_mem_map[entry].attrs = attrs;
215 debug("Added memory mapping (%d): %llx %llx\n", entry,
216 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
217 i++; entry++;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800218 }
Peng Fanb749b5e2019-08-27 06:25:27 +0000219
220 icache_enable();
221 dcache_enable();
222}
223
Peng Fanfa35c3d2020-07-09 15:26:06 +0800224__weak int board_phys_sdram_size(phys_size_t *size)
225{
226 if (!size)
227 return -EINVAL;
228
229 *size = PHYS_SDRAM_SIZE;
Ye Li453bfcb2022-04-07 15:55:56 +0800230
231#ifdef PHYS_SDRAM_2_SIZE
232 *size += PHYS_SDRAM_2_SIZE;
233#endif
Peng Fanfa35c3d2020-07-09 15:26:06 +0800234 return 0;
235}
236
237int dram_init(void)
238{
239 phys_size_t sdram_size;
240 int ret;
241
242 ret = board_phys_sdram_size(&sdram_size);
243 if (ret)
244 return ret;
245
246 /* rom_pointer[1] contains the size of TEE occupies */
Marek Vasut9ca966e2022-12-22 01:46:38 +0100247 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1])
Peng Fanfa35c3d2020-07-09 15:26:06 +0800248 gd->ram_size = sdram_size - rom_pointer[1];
249 else
250 gd->ram_size = sdram_size;
251
Peng Fanfa35c3d2020-07-09 15:26:06 +0800252 return 0;
253}
254
255int dram_init_banksize(void)
256{
257 int bank = 0;
258 int ret;
259 phys_size_t sdram_size;
Ye Li453bfcb2022-04-07 15:55:56 +0800260 phys_size_t sdram_b1_size, sdram_b2_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800261
262 ret = board_phys_sdram_size(&sdram_size);
263 if (ret)
264 return ret;
265
Ye Li453bfcb2022-04-07 15:55:56 +0800266 /* Bank 1 can't cross over 4GB space */
267 if (sdram_size > 0xc0000000) {
268 sdram_b1_size = 0xc0000000;
269 sdram_b2_size = sdram_size - 0xc0000000;
270 } else {
271 sdram_b1_size = sdram_size;
272 sdram_b2_size = 0;
273 }
274
Peng Fanfa35c3d2020-07-09 15:26:06 +0800275 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
Marek Vasut9ca966e2022-12-22 01:46:38 +0100276 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800277 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
278 phys_size_t optee_size = (size_t)rom_pointer[1];
279
280 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
Ye Li453bfcb2022-04-07 15:55:56 +0800281 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800282 if (++bank >= CONFIG_NR_DRAM_BANKS) {
283 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
284 return -1;
285 }
286
287 gd->bd->bi_dram[bank].start = optee_start + optee_size;
288 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
Ye Li453bfcb2022-04-07 15:55:56 +0800289 sdram_b1_size - gd->bd->bi_dram[bank].start;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800290 }
291 } else {
Ye Li453bfcb2022-04-07 15:55:56 +0800292 gd->bd->bi_dram[bank].size = sdram_b1_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800293 }
294
Ye Li453bfcb2022-04-07 15:55:56 +0800295 if (sdram_b2_size) {
296 if (++bank >= CONFIG_NR_DRAM_BANKS) {
297 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
298 return -1;
299 }
300 gd->bd->bi_dram[bank].start = 0x100000000UL;
301 gd->bd->bi_dram[bank].size = sdram_b2_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800302 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800303
304 return 0;
305}
306
307phys_size_t get_effective_memsize(void)
308{
Ye Li453bfcb2022-04-07 15:55:56 +0800309 int ret;
310 phys_size_t sdram_size;
311 phys_size_t sdram_b1_size;
312 ret = board_phys_sdram_size(&sdram_size);
313 if (!ret) {
314 /* Bank 1 can't cross over 4GB space */
315 if (sdram_size > 0xc0000000) {
316 sdram_b1_size = 0xc0000000;
317 } else {
318 sdram_b1_size = sdram_size;
319 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800320
Marek Vasut9ca966e2022-12-22 01:46:38 +0100321 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
Ye Li453bfcb2022-04-07 15:55:56 +0800322 /* We will relocate u-boot to Top of dram1. Tee position has two cases:
323 * 1. At the top of dram1, Then return the size removed optee size.
324 * 2. In the middle of dram1, return the size of dram1.
325 */
326 if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
327 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
328 }
329
330 return sdram_b1_size;
331 } else {
332 return PHYS_SDRAM_SIZE;
333 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800334}
335
Pali Rohár4f4f5832022-09-09 17:32:40 +0200336phys_size_t board_get_usable_ram_top(phys_size_t total_size)
Frieder Schrempf159879e2021-06-07 14:36:44 +0200337{
Marek Vasutdcbbf782022-04-14 15:51:46 +0200338 ulong top_addr;
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800339
Frieder Schrempf159879e2021-06-07 14:36:44 +0200340 /*
341 * Some IPs have their accessible address space restricted by
342 * the interconnect. Let's make sure U-Boot only ever uses the
343 * space below the 4G address boundary (which is 3GiB big),
344 * even when the effective available memory is bigger.
345 */
Marek Vasutdcbbf782022-04-14 15:51:46 +0200346 top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800347
348 /*
349 * rom_pointer[0] stores the TEE memory start address.
350 * rom_pointer[1] stores the size TEE uses.
351 * We need to reserve the memory region for TEE.
352 */
Marek Vasut9ca966e2022-12-22 01:46:38 +0100353 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
354 rom_pointer[1] && top_addr > rom_pointer[0])
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800355 top_addr = rom_pointer[0];
Frieder Schrempf159879e2021-06-07 14:36:44 +0200356
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800357 return top_addr;
Frieder Schrempf159879e2021-06-07 14:36:44 +0200358}
359
Peng Fan1caffdf2019-08-27 06:25:17 +0000360static u32 get_cpu_variant_type(u32 type)
361{
362 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
363 struct fuse_bank *bank = &ocotp->bank[1];
364 struct fuse_bank1_regs *fuse =
365 (struct fuse_bank1_regs *)bank->fuse_regs;
366
367 u32 value = readl(&fuse->tester4);
368
Peng Fan67815082020-02-05 17:34:54 +0800369 if (type == MXC_CPU_IMX8MQ) {
370 if ((value & 0x3) == 0x2)
371 return MXC_CPU_IMX8MD;
372 else if (value & 0x200000)
373 return MXC_CPU_IMX8MQL;
374
375 } else if (type == MXC_CPU_IMX8MM) {
Peng Fan1caffdf2019-08-27 06:25:17 +0000376 switch (value & 0x3) {
377 case 2:
378 if (value & 0x1c0000)
379 return MXC_CPU_IMX8MMDL;
380 else
381 return MXC_CPU_IMX8MMD;
382 case 3:
383 if (value & 0x1c0000)
384 return MXC_CPU_IMX8MMSL;
385 else
386 return MXC_CPU_IMX8MMS;
387 default:
388 if (value & 0x1c0000)
389 return MXC_CPU_IMX8MML;
390 break;
391 }
Peng Fan1a07d912020-02-05 17:39:27 +0800392 } else if (type == MXC_CPU_IMX8MN) {
393 switch (value & 0x3) {
394 case 2:
Ye Li715180e2021-03-19 15:57:11 +0800395 if (value & 0x1000000) {
396 if (value & 0x10000000) /* MIPI DSI */
397 return MXC_CPU_IMX8MNUD;
398 else
399 return MXC_CPU_IMX8MNDL;
400 } else {
Peng Fan1a07d912020-02-05 17:39:27 +0800401 return MXC_CPU_IMX8MND;
Ye Li715180e2021-03-19 15:57:11 +0800402 }
Peng Fan1a07d912020-02-05 17:39:27 +0800403 case 3:
Ye Li715180e2021-03-19 15:57:11 +0800404 if (value & 0x1000000) {
405 if (value & 0x10000000) /* MIPI DSI */
406 return MXC_CPU_IMX8MNUS;
407 else
408 return MXC_CPU_IMX8MNSL;
409 } else {
Peng Fan1a07d912020-02-05 17:39:27 +0800410 return MXC_CPU_IMX8MNS;
Ye Li715180e2021-03-19 15:57:11 +0800411 }
Peng Fan1a07d912020-02-05 17:39:27 +0800412 default:
Ye Li715180e2021-03-19 15:57:11 +0800413 if (value & 0x1000000) {
414 if (value & 0x10000000) /* MIPI DSI */
415 return MXC_CPU_IMX8MNUQ;
416 else
417 return MXC_CPU_IMX8MNL;
418 }
Peng Fan1a07d912020-02-05 17:39:27 +0800419 break;
420 }
Ye Lid2d754f2020-04-20 20:12:54 -0700421 } else if (type == MXC_CPU_IMX8MP) {
422 u32 value0 = readl(&fuse->tester3);
423 u32 flag = 0;
424
425 if ((value0 & 0xc0000) == 0x80000)
426 return MXC_CPU_IMX8MPD;
427
428 /* vpu disabled */
429 if ((value0 & 0x43000000) == 0x43000000)
430 flag = 1;
431
432 /* npu disabled*/
433 if ((value & 0x8) == 0x8)
Peng Fan0386e7f2022-04-07 15:55:52 +0800434 flag |= BIT(1);
Ye Lid2d754f2020-04-20 20:12:54 -0700435
436 /* isp disabled */
437 if ((value & 0x3) == 0x3)
Peng Fan0386e7f2022-04-07 15:55:52 +0800438 flag |= BIT(2);
439
440 /* gpu disabled */
441 if ((value & 0xc0) == 0xc0)
442 flag |= BIT(3);
443
444 /* lvds disabled */
445 if ((value & 0x180000) == 0x180000)
446 flag |= BIT(4);
447
448 /* mipi dsi disabled */
449 if ((value & 0x60000) == 0x60000)
450 flag |= BIT(5);
Ye Lid2d754f2020-04-20 20:12:54 -0700451
452 switch (flag) {
Peng Fan0386e7f2022-04-07 15:55:52 +0800453 case 0x3f:
454 return MXC_CPU_IMX8MPUL;
Ye Lid2d754f2020-04-20 20:12:54 -0700455 case 7:
456 return MXC_CPU_IMX8MPL;
Ye Lid2d754f2020-04-20 20:12:54 -0700457 case 2:
458 return MXC_CPU_IMX8MP6;
Ye Lid2d754f2020-04-20 20:12:54 -0700459 default:
460 break;
461 }
462
Peng Fan1caffdf2019-08-27 06:25:17 +0000463 }
464
465 return type;
466}
467
Peng Faneae4de22018-01-10 13:20:37 +0800468u32 get_cpu_rev(void)
469{
470 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
471 u32 reg = readl(&ana_pll->digprog);
472 u32 type = (reg >> 16) & 0xff;
Peng Fan1caffdf2019-08-27 06:25:17 +0000473 u32 major_low = (reg >> 8) & 0xff;
Peng Faneae4de22018-01-10 13:20:37 +0800474 u32 rom_version;
475
476 reg &= 0xff;
477
Peng Fan69cec072019-12-27 10:14:02 +0800478 /* iMX8MP */
479 if (major_low == 0x43) {
Ye Lid2d754f2020-04-20 20:12:54 -0700480 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
Peng Fan69cec072019-12-27 10:14:02 +0800481 } else if (major_low == 0x42) {
482 /* iMX8MN */
Peng Fan1a07d912020-02-05 17:39:27 +0800483 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
Peng Fan5d2f2062019-06-27 17:23:49 +0800484 } else if (major_low == 0x41) {
Peng Fan1caffdf2019-08-27 06:25:17 +0000485 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
486 } else {
487 if (reg == CHIP_REV_1_0) {
488 /*
Peng Fanc23fbdd2019-10-16 10:24:17 +0000489 * For B0 chip, the DIGPROG is not updated,
490 * it is still TO1.0. we have to check ROM
491 * version or OCOTP_READ_FUSE_DATA.
492 * 0xff0055aa is magic number for B1.
Peng Fan1caffdf2019-08-27 06:25:17 +0000493 */
Peng Fanc23fbdd2019-10-16 10:24:17 +0000494 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
Ye Lic963ed12021-03-19 15:57:16 +0800495 /*
496 * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
497 * so have to check ROM to distinguish them
498 */
499 rom_version = readl((void __iomem *)ROM_VERSION_B0);
500 rom_version &= 0xff;
501 if (rom_version == CHIP_REV_2_2)
502 reg = CHIP_REV_2_2;
503 else
504 reg = CHIP_REV_2_1;
Peng Fanc23fbdd2019-10-16 10:24:17 +0000505 } else {
506 rom_version =
507 readl((void __iomem *)ROM_VERSION_A0);
508 if (rom_version != CHIP_REV_1_0) {
509 rom_version = readl((void __iomem *)ROM_VERSION_B0);
Patrick Wildtd4a78b92019-11-19 09:42:06 +0100510 rom_version &= 0xff;
Peng Fanc23fbdd2019-10-16 10:24:17 +0000511 if (rom_version == CHIP_REV_2_0)
512 reg = CHIP_REV_2_0;
513 }
Peng Fan1caffdf2019-08-27 06:25:17 +0000514 }
Peng Faneae4de22018-01-10 13:20:37 +0800515 }
Peng Fan67815082020-02-05 17:34:54 +0800516
517 type = get_cpu_variant_type(type);
Peng Faneae4de22018-01-10 13:20:37 +0800518 }
519
520 return (type << 12) | reg;
521}
522
523static void imx_set_wdog_powerdown(bool enable)
524{
525 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
526 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
527 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
528
529 /* Write to the PDE (Power Down Enable) bit */
530 writew(enable, &wdog1->wmcr);
531 writew(enable, &wdog2->wmcr);
532 writew(enable, &wdog3->wmcr);
533}
534
Simon Glassfc557362022-03-04 08:43:05 -0700535static int imx8m_check_clock(void *ctx, struct event *event)
Peng Fanc98e0322019-08-27 06:25:58 +0000536{
537 struct udevice *dev;
538 int ret;
539
Peng Fan3c073342019-10-16 03:01:51 +0000540 if (CONFIG_IS_ENABLED(CLK)) {
541 ret = uclass_get_device_by_name(UCLASS_CLK,
542 "clock-controller@30380000",
543 &dev);
544 if (ret < 0) {
545 printf("Failed to find clock node. Check device tree\n");
546 return ret;
547 }
Peng Fanc98e0322019-08-27 06:25:58 +0000548 }
549
550 return 0;
551}
Simon Glass93074012023-05-04 16:50:45 -0600552EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
Peng Fanc98e0322019-08-27 06:25:58 +0000553
Marek Vasutf7b184e2022-09-19 21:37:07 +0200554static void imx8m_setup_snvs(void)
555{
556 /* Enable SNVS clock */
557 clock_enable(CCGR_SNVS, 1);
558 /* Initialize glitch detect */
559 writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
560 /* Clear interrupt status */
561 writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
562}
563
Marek Vasut829858a2022-12-22 01:46:42 +0100564static void imx8m_setup_csu_tzasc(void)
565{
566 const uintptr_t tzasc_base[4] = {
567 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
568 };
569 int i, j;
570
571 if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
572 return;
573
574 /* CSU */
575 for (i = 0; i < 64; i++)
576 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
577
578 /* TZASC */
579 for (j = 0; j < 4; j++) {
580 writel(0x77777777, (void *)(tzasc_base[j]));
581 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
582 for (i = 0; i <= 0x10; i += 4)
583 writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
584 }
585}
586
Peng Faneae4de22018-01-10 13:20:37 +0800587int arch_cpu_init(void)
588{
Peng Fanc0b30d72019-04-17 09:41:16 +0000589 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
Marek Vasut3ea500a2022-04-13 00:41:52 +0200590
591#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
592 icache_enable();
593#endif
594
Peng Faneae4de22018-01-10 13:20:37 +0800595 /*
Peng Fand0ca2892019-08-27 06:25:37 +0000596 * ROM might disable clock for SCTR,
597 * enable the clock before timer_init.
598 */
599 if (IS_ENABLED(CONFIG_SPL_BUILD))
600 clock_enable(CCGR_SCTR, 1);
601 /*
Peng Faneae4de22018-01-10 13:20:37 +0800602 * Init timer at very early state, because sscg pll setting
603 * will use it
604 */
605 timer_init();
606
607 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
608 clock_init();
609 imx_set_wdog_powerdown(false);
Peng Fan9cf2aa32020-07-09 13:52:41 +0800610
611 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
612 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
Ye Li715180e2021-03-19 15:57:11 +0800613 is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
Peng Fan9cf2aa32020-07-09 13:52:41 +0800614 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
615 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
616 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
617 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
618 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
619
620 writel(0x1, &pgc_core2->pgcr);
621 writel(0x1, &pgc_core3->pgcr);
Ye Li715180e2021-03-19 15:57:11 +0800622 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
Peng Fan9cf2aa32020-07-09 13:52:41 +0800623 writel(0x1, &pgc_core1->pgcr);
624 writel(0xE, &gpc->cpu_pgc_dn_trg);
625 } else {
626 writel(0xC, &gpc->cpu_pgc_dn_trg);
627 }
628 }
Peng Faneae4de22018-01-10 13:20:37 +0800629 }
630
Peng Fanc0b30d72019-04-17 09:41:16 +0000631 if (is_imx8mq()) {
632 clock_enable(CCGR_OCOTP, 1);
633 if (readl(&ocotp->ctrl) & 0x200)
634 writel(0x200, &ocotp->ctrl_clr);
635 }
636
Marek Vasutf7b184e2022-09-19 21:37:07 +0200637 imx8m_setup_snvs();
638
Marek Vasut829858a2022-12-22 01:46:42 +0100639 imx8m_setup_csu_tzasc();
640
Peng Faneae4de22018-01-10 13:20:37 +0800641 return 0;
642}
643
Peng Fanc9823b02019-09-16 03:09:36 +0000644#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
645struct rom_api *g_rom_api = (struct rom_api *)0x980;
Peng Fanc9823b02019-09-16 03:09:36 +0000646#endif
647
Marek Vasut520ded02021-07-03 04:55:33 +0200648#if defined(CONFIG_IMX8M)
649#include <spl.h>
650int spl_mmc_emmc_boot_partition(struct mmc *mmc)
651{
652 u32 *rom_log_addr = (u32 *)0x9e0;
653 u32 *rom_log;
654 u8 event_id;
655 int i, part;
656
657 part = default_spl_mmc_emmc_boot_partition(mmc);
658
659 /* If the ROM event log pointer is not valid. */
660 if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
661 *rom_log_addr & 0x3)
662 return part;
663
664 /* Parse the ROM event ID version 2 log */
665 rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
666 for (i = 0; i < 128; i++) {
667 event_id = rom_log[i] >> 24;
668 switch (event_id) {
669 case 0x00: /* End of list */
670 return part;
671 /* Log entries with 1 parameter, skip 1 */
672 case 0x80: /* Start to perform the device initialization */
673 case 0x81: /* The boot device initialization completes */
674 case 0x8f: /* The boot device initialization fails */
675 case 0x90: /* Start to read data from boot device */
676 case 0x91: /* Reading data from boot device completes */
677 case 0x9f: /* Reading data from boot device fails */
678 i += 1;
679 continue;
680 /* Log entries with 2 parameters, skip 2 */
681 case 0xa0: /* Image authentication result */
682 case 0xc0: /* Jump to the boot image soon */
683 i += 2;
684 continue;
685 /* Boot from the secondary boot image */
686 case 0x51:
687 /*
688 * Swap the eMMC boot partitions in case there was a
689 * fallback event (i.e. primary image was corrupted
690 * and that corruption was recognized by the BootROM),
691 * so the SPL loads the rest of the U-Boot from the
692 * correct eMMC boot partition, since the BootROM
693 * leaves the boot partition set to the corrupted one.
694 */
695 if (part == 1)
696 part = 2;
697 else if (part == 2)
698 part = 1;
699 continue;
700 default:
701 continue;
702 }
703 }
704
705 return part;
706}
707#endif
708
Peng Faneae4de22018-01-10 13:20:37 +0800709bool is_usb_boot(void)
710{
711 return get_boot_device() == USB_BOOT;
712}
713
714#ifdef CONFIG_OF_SYSTEM_SETUP
Peng Fan435dc122020-07-09 14:06:49 +0800715bool check_fdt_new_path(void *blob)
716{
717 const char *soc_path = "/soc@0";
718 int nodeoff;
719
720 nodeoff = fdt_path_offset(blob, soc_path);
721 if (nodeoff < 0)
722 return false;
723
724 return true;
725}
726
727static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
728{
729 int i = 0;
730 int rc;
731 int nodeoff;
732 const char *status = "disabled";
733
734 for (i = 0; i < size_array; i++) {
735 nodeoff = fdt_path_offset(blob, nodes_path[i]);
736 if (nodeoff < 0)
737 continue; /* Not found, skip it */
738
739 printf("Found %s node\n", nodes_path[i]);
740
741add_status:
742 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
743 if (rc) {
744 if (rc == -FDT_ERR_NOSPACE) {
745 rc = fdt_increase_size(blob, 512);
746 if (!rc)
747 goto add_status;
748 }
749 printf("Unable to update property %s:%s, err=%s\n",
750 nodes_path[i], "status", fdt_strerror(rc));
751 } else {
752 printf("Modify %s:%s disabled\n",
753 nodes_path[i], "status");
754 }
755 }
756
757 return 0;
758}
759
760#ifdef CONFIG_IMX8MQ
761bool check_dcss_fused(void)
762{
763 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
764 struct fuse_bank *bank = &ocotp->bank[1];
765 struct fuse_bank1_regs *fuse =
766 (struct fuse_bank1_regs *)bank->fuse_regs;
767 u32 value = readl(&fuse->tester4);
768
769 if (value & 0x4000000)
770 return true;
771
772 return false;
773}
774
775static int disable_mipi_dsi_nodes(void *blob)
776{
777 static const char * const nodes_path[] = {
778 "/mipi_dsi@30A00000",
779 "/mipi_dsi_bridge@30A00000",
780 "/dsi_phy@30A00300",
781 "/soc@0/bus@30800000/mipi_dsi@30a00000",
Peng Fan7d4195c2021-03-19 15:57:13 +0800782 "/soc@0/bus@30800000/dphy@30a00300",
783 "/soc@0/bus@30800000/mipi-dsi@30a00000",
Peng Fan435dc122020-07-09 14:06:49 +0800784 };
785
786 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
787}
788
789static int disable_dcss_nodes(void *blob)
790{
791 static const char * const nodes_path[] = {
792 "/dcss@0x32e00000",
793 "/dcss@32e00000",
794 "/hdmi@32c00000",
795 "/hdmi_cec@32c33800",
796 "/hdmi_drm@32c00000",
797 "/display-subsystem",
798 "/sound-hdmi",
799 "/sound-hdmi-arc",
800 "/soc@0/bus@32c00000/display-controller@32e00000",
801 "/soc@0/bus@32c00000/hdmi@32c00000",
802 };
803
804 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
805}
806
807static int check_mipi_dsi_nodes(void *blob)
808{
809 static const char * const lcdif_path[] = {
810 "/lcdif@30320000",
Peng Fan7d4195c2021-03-19 15:57:13 +0800811 "/soc@0/bus@30000000/lcdif@30320000",
812 "/soc@0/bus@30000000/lcd-controller@30320000"
Peng Fan435dc122020-07-09 14:06:49 +0800813 };
814 static const char * const mipi_dsi_path[] = {
815 "/mipi_dsi@30A00000",
816 "/soc@0/bus@30800000/mipi_dsi@30a00000"
817 };
818 static const char * const lcdif_ep_path[] = {
819 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
Peng Fan7d4195c2021-03-19 15:57:13 +0800820 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
821 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
Peng Fan435dc122020-07-09 14:06:49 +0800822 };
823 static const char * const mipi_dsi_ep_path[] = {
824 "/mipi_dsi@30A00000/port@1/endpoint",
Peng Fan7d4195c2021-03-19 15:57:13 +0800825 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
826 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
Peng Fan435dc122020-07-09 14:06:49 +0800827 };
828
829 int lookup_node;
830 int nodeoff;
831 bool new_path = check_fdt_new_path(blob);
832 int i = new_path ? 1 : 0;
833
834 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
835 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
836 /*
837 * If can't find lcdif node or lcdif node is disabled,
838 * then disable all mipi dsi, since they only can input
839 * from DCSS
840 */
841 return disable_mipi_dsi_nodes(blob);
842 }
843
844 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
845 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
846 return 0;
847
848 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
849 if (nodeoff < 0) {
850 /*
851 * If can't find lcdif endpoint, then disable all mipi dsi,
852 * since they only can input from DCSS
853 */
854 return disable_mipi_dsi_nodes(blob);
855 }
856
857 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
858 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
859
860 if (nodeoff > 0 && nodeoff == lookup_node)
861 return 0;
862
863 return disable_mipi_dsi_nodes(blob);
864}
865#endif
866
867int disable_vpu_nodes(void *blob)
868{
869 static const char * const nodes_path_8mq[] = {
870 "/vpu@38300000",
871 "/soc@0/vpu@38300000"
872 };
873
874 static const char * const nodes_path_8mm[] = {
875 "/vpu_g1@38300000",
876 "/vpu_g2@38310000",
877 "/vpu_h1@38320000"
878 };
879
880 static const char * const nodes_path_8mp[] = {
881 "/vpu_g1@38300000",
882 "/vpu_g2@38310000",
883 "/vpu_vc8000e@38320000"
884 };
885
886 if (is_imx8mq())
887 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
888 else if (is_imx8mm())
889 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
890 else if (is_imx8mp())
891 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
892 else
893 return -EPERM;
894}
895
Ye Liee337ce2021-03-19 15:57:09 +0800896#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
897static int low_drive_gpu_freq(void *blob)
898{
899 static const char *nodes_path_8mn[] = {
900 "/gpu@38000000",
901 "/soc@0/gpu@38000000"
902 };
903
904 int nodeoff, cnt, i;
905 u32 assignedclks[7];
906
907 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
908 if (nodeoff < 0)
909 return nodeoff;
910
911 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
912 if (cnt < 0)
913 return cnt;
914
915 if (cnt != 7)
916 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
Heinrich Schuchardt72c891f2023-04-18 01:37:21 +0200917 if (cnt < 2)
918 return -1;
Ye Liee337ce2021-03-19 15:57:09 +0800919
920 assignedclks[cnt - 1] = 200000000;
921 assignedclks[cnt - 2] = 200000000;
922
923 for (i = 0; i < cnt; i++) {
924 debug("<%u>, ", assignedclks[i]);
925 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
926 }
927 debug("\n");
928
929 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
930}
931#endif
932
Peng Fanf5f9b8e2022-04-07 15:55:53 +0800933static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
934{
935 int lookup_node;
936 int nodeoff;
937
938 nodeoff = fdt_path_offset(blob, ep1);
939 if (nodeoff) {
940 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
941 nodeoff = fdt_path_offset(blob, ep2);
942
943 if (nodeoff > 0 && nodeoff == lookup_node)
944 return true;
945 }
946
947 return false;
948}
949
950int disable_dsi_lcdif_nodes(void *blob)
951{
952 int ret;
953
954 static const char * const dsi_path_8mp[] = {
955 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
956 };
957
958 static const char * const lcdif_path_8mp[] = {
959 "/soc@0/bus@32c00000/lcd-controller@32e80000"
960 };
961
962 static const char * const lcdif_ep_path_8mp[] = {
963 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
964 };
965 static const char * const dsi_ep_path_8mp[] = {
966 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
967 };
968
969 ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
970 if (ret)
971 return ret;
972
973 if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
974 /* Disable lcdif node */
975 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
976 }
977
978 return 0;
979}
980
981int disable_lvds_lcdif_nodes(void *blob)
982{
983 int ret, i;
984
985 static const char * const ldb_path_8mp[] = {
986 "/soc@0/bus@32c00000/ldb@32ec005c",
987 "/soc@0/bus@32c00000/phy@32ec0128"
988 };
989
990 static const char * const lcdif_path_8mp[] = {
991 "/soc@0/bus@32c00000/lcd-controller@32e90000"
992 };
993
994 static const char * const lcdif_ep_path_8mp[] = {
995 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
996 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
997 };
998 static const char * const ldb_ep_path_8mp[] = {
999 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1000 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1001 };
1002
1003 ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1004 if (ret)
1005 return ret;
1006
1007 for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1008 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1009 /* Disable lcdif node */
1010 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1011 }
1012 }
1013
1014 return 0;
1015}
1016
Peng Fan435dc122020-07-09 14:06:49 +08001017int disable_gpu_nodes(void *blob)
1018{
1019 static const char * const nodes_path_8mn[] = {
Peng Fan7d4195c2021-03-19 15:57:13 +08001020 "/gpu@38000000",
1021 "/soc@/gpu@38000000"
Peng Fan435dc122020-07-09 14:06:49 +08001022 };
1023
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001024 static const char * const nodes_path_8mp[] = {
1025 "/gpu3d@38000000",
1026 "/gpu2d@38008000"
1027 };
1028
1029 if (is_imx8mp())
1030 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1031 else
1032 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
Peng Fan435dc122020-07-09 14:06:49 +08001033}
1034
1035int disable_npu_nodes(void *blob)
1036{
1037 static const char * const nodes_path_8mp[] = {
1038 "/vipsi@38500000"
1039 };
1040
1041 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1042}
1043
1044int disable_isp_nodes(void *blob)
1045{
1046 static const char * const nodes_path_8mp[] = {
1047 "/soc@0/bus@32c00000/camera/isp@32e10000",
1048 "/soc@0/bus@32c00000/camera/isp@32e20000"
1049 };
1050
1051 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1052}
1053
1054int disable_dsp_nodes(void *blob)
1055{
1056 static const char * const nodes_path_8mp[] = {
1057 "/dsp@3b6e8000"
1058 };
1059
1060 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1061}
1062
Ye Li26517af2021-03-19 15:57:12 +08001063static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1064{
1065 static const char * const thermal_path[] = {
1066 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1067 };
1068
1069 int nodeoff, cnt, i, ret, j;
1070 u32 cooling_dev[12];
1071
1072 for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1073 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1074 if (nodeoff < 0)
1075 continue; /* Not found, skip it */
1076
1077 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1078 if (cnt < 0)
1079 continue;
1080
1081 if (cnt != 12)
1082 printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1083
1084 for (j = 0; j < cnt; j++)
1085 cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1086
1087 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1088 sizeof(u32) * (12 - disabled_cores * 3));
1089 if (ret < 0) {
1090 printf("Warning: %s, cooling-device setprop failed %d\n",
1091 thermal_path[i], ret);
1092 continue;
1093 }
1094
1095 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1096 }
1097}
1098
1099static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1100{
1101 static const char * const pmu_path[] = {
1102 "/pmu"
1103 };
1104
1105 int nodeoff, cnt, i, ret, j;
1106 u32 irq_affinity[4];
1107
1108 for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1109 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1110 if (nodeoff < 0)
1111 continue; /* Not found, skip it */
1112
1113 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1114 irq_affinity, 4);
1115 if (cnt < 0)
1116 continue;
1117
1118 if (cnt != 4)
1119 printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1120
1121 for (j = 0; j < cnt; j++)
1122 irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1123
1124 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1125 sizeof(u32) * (4 - disabled_cores));
1126 if (ret < 0) {
1127 printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1128 pmu_path[i], ret);
1129 continue;
1130 }
1131
1132 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1133 }
1134}
1135
Peng Fan435dc122020-07-09 14:06:49 +08001136static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1137{
1138 static const char * const nodes_path[] = {
1139 "/cpus/cpu@1",
1140 "/cpus/cpu@2",
1141 "/cpus/cpu@3",
1142 };
1143 u32 i = 0;
1144 int rc;
1145 int nodeoff;
1146
1147 if (disabled_cores > 3)
1148 return -EINVAL;
1149
1150 i = 3 - disabled_cores;
1151
1152 for (; i < 3; i++) {
1153 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1154 if (nodeoff < 0)
1155 continue; /* Not found, skip it */
1156
1157 debug("Found %s node\n", nodes_path[i]);
1158
1159 rc = fdt_del_node(blob, nodeoff);
1160 if (rc < 0) {
1161 printf("Unable to delete node %s, err=%s\n",
1162 nodes_path[i], fdt_strerror(rc));
1163 } else {
1164 printf("Delete node %s\n", nodes_path[i]);
1165 }
1166 }
1167
Ye Li26517af2021-03-19 15:57:12 +08001168 disable_thermal_cpu_nodes(blob, disabled_cores);
1169 disable_pmu_cpu_nodes(blob, disabled_cores);
1170
Peng Fan435dc122020-07-09 14:06:49 +08001171 return 0;
1172}
1173
Peng Fana08bc872022-04-07 15:55:54 +08001174static int cleanup_nodes_for_efi(void *blob)
1175{
Peng Fan1585b202022-04-07 15:55:55 +08001176 static const char * const path[][2] = {
1177 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1178 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1179 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1180 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1181 };
Peng Fana08bc872022-04-07 15:55:54 +08001182 int nodeoff, i, rc;
1183
Peng Fan1585b202022-04-07 15:55:55 +08001184 for (i = 0; i < ARRAY_SIZE(path); i++) {
1185 nodeoff = fdt_path_offset(blob, path[i][0]);
Peng Fana08bc872022-04-07 15:55:54 +08001186 if (nodeoff < 0)
1187 continue; /* Not found, skip it */
Peng Fan1585b202022-04-07 15:55:55 +08001188 debug("Found %s node\n", path[i][0]);
Peng Fana08bc872022-04-07 15:55:54 +08001189
Peng Fan1585b202022-04-07 15:55:55 +08001190 rc = fdt_delprop(blob, nodeoff, path[i][1]);
Peng Fana08bc872022-04-07 15:55:54 +08001191 if (rc == -FDT_ERR_NOTFOUND)
1192 continue;
1193 if (rc) {
1194 printf("Unable to update property %s:%s, err=%s\n",
Peng Fan1585b202022-04-07 15:55:55 +08001195 path[i][0], path[i][1], fdt_strerror(rc));
Peng Fana08bc872022-04-07 15:55:54 +08001196 return rc;
1197 }
1198
Peng Fan1585b202022-04-07 15:55:55 +08001199 printf("Remove %s:%s\n", path[i][0], path[i][1]);
Peng Fana08bc872022-04-07 15:55:54 +08001200 }
1201
1202 return 0;
1203}
Peng Fana08bc872022-04-07 15:55:54 +08001204
Andrejs Cainikovs2f3491c2022-05-27 15:20:42 +02001205static int fixup_thermal_trips(void *blob, const char *name)
1206{
1207 int minc, maxc;
1208 int node, trip;
1209
1210 node = fdt_path_offset(blob, "/thermal-zones");
1211 if (node < 0)
1212 return node;
1213
1214 node = fdt_subnode_offset(blob, node, name);
1215 if (node < 0)
1216 return node;
1217
1218 node = fdt_subnode_offset(blob, node, "trips");
1219 if (node < 0)
1220 return node;
1221
1222 get_cpu_temp_grade(&minc, &maxc);
1223
1224 fdt_for_each_subnode(trip, blob, node) {
1225 const char *type;
1226 int temp, ret;
1227
1228 type = fdt_getprop(blob, trip, "type", NULL);
1229 if (!type)
1230 continue;
1231
1232 temp = 0;
1233 if (!strcmp(type, "critical"))
1234 temp = 1000 * maxc;
1235 else if (!strcmp(type, "passive"))
1236 temp = 1000 * (maxc - 10);
1237 if (temp) {
1238 ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1239 if (ret)
1240 return ret;
1241 }
1242 }
1243
1244 return 0;
1245}
1246
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001247int ft_system_setup(void *blob, struct bd_info *bd)
Peng Faneae4de22018-01-10 13:20:37 +08001248{
Peng Fan435dc122020-07-09 14:06:49 +08001249#ifdef CONFIG_IMX8MQ
Peng Faneae4de22018-01-10 13:20:37 +08001250 int i = 0;
1251 int rc;
1252 int nodeoff;
1253
Peng Fan435dc122020-07-09 14:06:49 +08001254 if (get_boot_device() == USB_BOOT) {
1255 disable_dcss_nodes(blob);
1256
1257 bool new_path = check_fdt_new_path(blob);
1258 int v = new_path ? 1 : 0;
1259 static const char * const usb_dwc3_path[] = {
1260 "/usb@38100000/dwc3",
1261 "/soc@0/usb@38100000"
1262 };
1263
1264 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1265 if (nodeoff >= 0) {
1266 const char *speed = "high-speed";
1267
1268 printf("Found %s node\n", usb_dwc3_path[v]);
1269
1270usb_modify_speed:
1271
1272 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1273 if (rc) {
1274 if (rc == -FDT_ERR_NOSPACE) {
1275 rc = fdt_increase_size(blob, 512);
1276 if (!rc)
1277 goto usb_modify_speed;
1278 }
1279 printf("Unable to set property %s:%s, err=%s\n",
1280 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1281 } else {
1282 printf("Modify %s:%s = %s\n",
1283 usb_dwc3_path[v], "maximum-speed", speed);
1284 }
1285 } else {
1286 printf("Can't found %s node\n", usb_dwc3_path[v]);
1287 }
1288 }
1289
Peng Faneae4de22018-01-10 13:20:37 +08001290 /* Disable the CPU idle for A0 chip since the HW does not support it */
1291 if (is_soc_rev(CHIP_REV_1_0)) {
1292 static const char * const nodes_path[] = {
1293 "/cpus/cpu@0",
1294 "/cpus/cpu@1",
1295 "/cpus/cpu@2",
1296 "/cpus/cpu@3",
1297 };
1298
1299 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1300 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1301 if (nodeoff < 0)
1302 continue; /* Not found, skip it */
1303
Marek Vasute2e7a772020-04-24 21:37:33 +02001304 debug("Found %s node\n", nodes_path[i]);
Peng Faneae4de22018-01-10 13:20:37 +08001305
1306 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
Marek Vasute2e7a772020-04-24 21:37:33 +02001307 if (rc == -FDT_ERR_NOTFOUND)
1308 continue;
Peng Faneae4de22018-01-10 13:20:37 +08001309 if (rc) {
1310 printf("Unable to update property %s:%s, err=%s\n",
1311 nodes_path[i], "status", fdt_strerror(rc));
1312 return rc;
1313 }
1314
Marek Vasute2e7a772020-04-24 21:37:33 +02001315 debug("Remove %s:%s\n", nodes_path[i],
Peng Faneae4de22018-01-10 13:20:37 +08001316 "cpu-idle-states");
1317 }
1318 }
1319
Peng Fan435dc122020-07-09 14:06:49 +08001320 if (is_imx8mql()) {
1321 disable_vpu_nodes(blob);
1322 if (check_dcss_fused()) {
1323 printf("DCSS is fused\n");
1324 disable_dcss_nodes(blob);
1325 check_mipi_dsi_nodes(blob);
1326 }
1327 }
1328
1329 if (is_imx8md())
1330 disable_cpu_nodes(blob, 2);
1331
1332#elif defined(CONFIG_IMX8MM)
1333 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
1334 disable_vpu_nodes(blob);
1335
1336 if (is_imx8mmd() || is_imx8mmdl())
1337 disable_cpu_nodes(blob, 2);
1338 else if (is_imx8mms() || is_imx8mmsl())
1339 disable_cpu_nodes(blob, 3);
1340
1341#elif defined(CONFIG_IMX8MN)
1342 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1343 disable_gpu_nodes(blob);
Ye Liee337ce2021-03-19 15:57:09 +08001344#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1345 else {
1346 int ldm_gpu = low_drive_gpu_freq(blob);
1347
1348 if (ldm_gpu < 0)
1349 printf("Update GPU node assigned-clock-rates failed\n");
1350 else
1351 printf("Update GPU node assigned-clock-rates ok\n");
1352 }
1353#endif
Peng Fan435dc122020-07-09 14:06:49 +08001354
Ye Li715180e2021-03-19 15:57:11 +08001355 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
Peng Fan435dc122020-07-09 14:06:49 +08001356 disable_cpu_nodes(blob, 2);
Ye Li715180e2021-03-19 15:57:11 +08001357 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
Peng Fan435dc122020-07-09 14:06:49 +08001358 disable_cpu_nodes(blob, 3);
1359
1360#elif defined(CONFIG_IMX8MP)
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001361 if (is_imx8mpul()) {
1362 /* Disable GPU */
1363 disable_gpu_nodes(blob);
1364
1365 /* Disable DSI */
1366 disable_dsi_lcdif_nodes(blob);
1367
1368 /* Disable LVDS */
1369 disable_lvds_lcdif_nodes(blob);
1370 }
1371
1372 if (is_imx8mpul() || is_imx8mpl())
Peng Fan435dc122020-07-09 14:06:49 +08001373 disable_vpu_nodes(blob);
1374
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001375 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
Peng Fan435dc122020-07-09 14:06:49 +08001376 disable_npu_nodes(blob);
1377
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001378 if (is_imx8mpul() || is_imx8mpl())
Peng Fan435dc122020-07-09 14:06:49 +08001379 disable_isp_nodes(blob);
1380
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001381 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
Peng Fan435dc122020-07-09 14:06:49 +08001382 disable_dsp_nodes(blob);
1383
1384 if (is_imx8mpd())
1385 disable_cpu_nodes(blob, 2);
1386#endif
1387
Peng Fan1585b202022-04-07 15:55:55 +08001388 cleanup_nodes_for_efi(blob);
Andrejs Cainikovs2f3491c2022-05-27 15:20:42 +02001389
1390 if (fixup_thermal_trips(blob, "cpu-thermal"))
1391 printf("Failed to update cpu-thermal trip(s)");
1392 if (IS_ENABLED(CONFIG_IMX8MP) &&
1393 fixup_thermal_trips(blob, "soc-thermal"))
1394 printf("Failed to update soc-thermal trip(s)");
1395
Peng Faneae4de22018-01-10 13:20:37 +08001396 return 0;
1397}
1398#endif
1399
Marek Vasut64dc4de2020-04-29 15:04:21 +02001400#if !CONFIG_IS_ENABLED(SYSRESET)
Harald Seiler6f14d5f2020-12-15 16:47:52 +01001401void reset_cpu(void)
Peng Faneae4de22018-01-10 13:20:37 +08001402{
Claudius Heinee73f3942020-04-29 15:04:23 +02001403 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
Peng Faneae4de22018-01-10 13:20:37 +08001404
Ye Li54a915a2019-12-09 00:47:18 -08001405 /* Clear WDA to trigger WDOG_B immediately */
1406 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
Peng Fan24290d92019-08-27 06:25:41 +00001407
Ye Li54a915a2019-12-09 00:47:18 -08001408 while (1) {
1409 /*
Harald Seilerec0c4472020-04-29 15:04:22 +02001410 * spin for .5 seconds before reset
Ye Li54a915a2019-12-09 00:47:18 -08001411 */
1412 }
Peng Faneae4de22018-01-10 13:20:37 +08001413}
Peng Fan24290d92019-08-27 06:25:41 +00001414#endif
Peng Fan5760d8d2020-04-22 10:51:13 +08001415
1416#if defined(CONFIG_ARCH_MISC_INIT)
Peng Fan5760d8d2020-04-22 10:51:13 +08001417int arch_misc_init(void)
1418{
Gaurav Jain81113a02022-03-24 11:50:27 +05301419 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1420 struct udevice *dev;
1421 int ret;
1422
1423 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1424 if (ret)
Ye Liec346892022-05-11 13:56:20 +05301425 printf("Failed to initialize caam_jr: %d\n", ret);
Gaurav Jain81113a02022-03-24 11:50:27 +05301426 }
Peng Fan5760d8d2020-04-22 10:51:13 +08001427
1428 return 0;
1429}
1430#endif
Ye Li325cd012020-05-03 22:19:52 +08001431
1432void imx_tmu_arch_init(void *reg_base)
1433{
Ye Lia00f2f02020-05-03 22:19:53 +08001434 if (is_imx8mm() || is_imx8mn()) {
Ye Li325cd012020-05-03 22:19:52 +08001435 /* Load TCALIV and TASR from fuses */
1436 struct ocotp_regs *ocotp =
1437 (struct ocotp_regs *)OCOTP_BASE_ADDR;
1438 struct fuse_bank *bank = &ocotp->bank[3];
1439 struct fuse_bank3_regs *fuse =
1440 (struct fuse_bank3_regs *)bank->fuse_regs;
1441
1442 u32 tca_rt, tca_hr, tca_en;
1443 u32 buf_vref, buf_slope;
1444
1445 tca_rt = fuse->ana0 & 0xFF;
1446 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
1447 tca_en = (fuse->ana0 & 0x2000000) >> 25;
1448
1449 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
1450 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
1451
1452 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1453 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
1454 (ulong)reg_base + 0x30);
1455 }
Ye Li41a20252020-05-03 22:19:54 +08001456#ifdef CONFIG_IMX8MP
1457 /* Load TCALIV0/1/m40 and TRIM from fuses */
1458 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1459 struct fuse_bank *bank = &ocotp->bank[38];
1460 struct fuse_bank38_regs *fuse =
1461 (struct fuse_bank38_regs *)bank->fuse_regs;
1462 struct fuse_bank *bank2 = &ocotp->bank[39];
1463 struct fuse_bank39_regs *fuse2 =
1464 (struct fuse_bank39_regs *)bank2->fuse_regs;
1465 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
1466 u32 reg;
1467 u32 tca40[2], tca25[2], tca105[2];
1468
1469 /* For blank sample */
1470 if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
1471 !fuse->ana_trim4 && !fuse2->ana_trim5) {
1472 /* Use a default 25C binary codes */
1473 tca25[0] = 1596;
Ye Lid756ca02020-05-03 22:19:55 +08001474 tca25[1] = 1596;
Ye Li41a20252020-05-03 22:19:54 +08001475 writel(tca25[0], (ulong)reg_base + 0x30);
Ye Lid756ca02020-05-03 22:19:55 +08001476 writel(tca25[1], (ulong)reg_base + 0x34);
Ye Li41a20252020-05-03 22:19:54 +08001477 return;
1478 }
1479
1480 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
1481 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1482 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1483 bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1484 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1485 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1486
1487 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
1488 writel(reg, (ulong)reg_base + 0x3c);
1489
1490 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1491 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1492 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1493 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1494 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1495 tca25[1] = fuse2->ana_trim5 & 0xFFF;
1496 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1497
1498 /* use 25c for 1p calibration */
1499 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1500 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1501 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1502#endif
Ye Li325cd012020-05-03 22:19:52 +08001503}
Peng Fana35215d2020-07-09 13:39:26 +08001504
1505#if defined(CONFIG_SPL_BUILD)
1506#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1507bool serror_need_skip = true;
1508
Sean Anderson2d755492022-03-22 17:17:35 -04001509void do_error(struct pt_regs *pt_regs)
Peng Fana35215d2020-07-09 13:39:26 +08001510{
1511 /*
1512 * If stack is still in ROM reserved OCRAM not switch to SPL,
1513 * it is the ROM SError
1514 */
1515 ulong sp;
1516
1517 asm volatile("mov %0, sp" : "=r"(sp) : );
1518
1519 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1520 /* Check for ERR050342, imx8mq HDCP enabled parts */
1521 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1522 serror_need_skip = false;
1523 return; /* Do nothing skip the SError in ROM */
1524 }
1525
1526 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1527 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1528 serror_need_skip = false;
1529 return; /* Do nothing skip the SError in ROM */
1530 }
1531 }
1532
1533 efi_restore_gd();
Sean Anderson2d755492022-03-22 17:17:35 -04001534 printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
Peng Fana35215d2020-07-09 13:39:26 +08001535 show_regs(pt_regs);
1536 panic("Resetting CPU ...\n");
1537}
1538#endif
1539#endif
Ye Li0513f362019-07-15 01:16:46 -07001540
1541#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
Marek Vasut765b5802022-04-06 02:21:34 +02001542enum env_location arch_env_get_location(enum env_operation op, int prio)
Ye Li0513f362019-07-15 01:16:46 -07001543{
1544 enum boot_device dev = get_boot_device();
Ye Li0513f362019-07-15 01:16:46 -07001545
1546 if (prio)
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001547 return ENVL_UNKNOWN;
Ye Li0513f362019-07-15 01:16:46 -07001548
1549 switch (dev) {
Fabio Estevam9be6daf2022-04-21 15:05:23 -03001550 case USB_BOOT:
1551 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1552 return ENVL_SPI_FLASH;
1553 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1554 return ENVL_NAND;
1555 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1556 return ENVL_MMC;
1557 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1558 return ENVL_NOWHERE;
1559 return ENVL_UNKNOWN;
Ye Li0513f362019-07-15 01:16:46 -07001560 case QSPI_BOOT:
Marek Vasut31b3bc42022-03-25 18:59:28 +01001561 case SPI_NOR_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001562 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1563 return ENVL_SPI_FLASH;
1564 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001565 case NAND_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001566 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1567 return ENVL_NAND;
1568 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001569 case SD1_BOOT:
1570 case SD2_BOOT:
1571 case SD3_BOOT:
1572 case MMC1_BOOT:
1573 case MMC2_BOOT:
1574 case MMC3_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001575 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1576 return ENVL_MMC;
1577 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1578 return ENVL_EXT4;
1579 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1580 return ENVL_FAT;
1581 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001582 default:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001583 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001584 }
Ye Li0513f362019-07-15 01:16:46 -07001585}
1586
Ye Li0513f362019-07-15 01:16:46 -07001587#endif
Peng Fanf19e0e52022-04-29 16:03:14 +08001588
1589#ifdef CONFIG_IMX_BOOTAUX
1590const struct rproc_att hostmap[] = {
1591 /* aux core , host core, size */
1592 { 0x00000000, 0x007e0000, 0x00020000 },
1593 /* OCRAM_S */
1594 { 0x00180000, 0x00180000, 0x00008000 },
1595 /* OCRAM */
1596 { 0x00900000, 0x00900000, 0x00020000 },
1597 /* OCRAM */
1598 { 0x00920000, 0x00920000, 0x00020000 },
1599 /* QSPI Code - alias */
1600 { 0x08000000, 0x08000000, 0x08000000 },
1601 /* DDR (Code) - alias */
1602 { 0x10000000, 0x80000000, 0x0FFE0000 },
1603 /* TCML */
1604 { 0x1FFE0000, 0x007E0000, 0x00040000 },
1605 /* OCRAM_S */
1606 { 0x20180000, 0x00180000, 0x00008000 },
1607 /* OCRAM */
1608 { 0x20200000, 0x00900000, 0x00040000 },
1609 /* DDR (Data) */
1610 { 0x40000000, 0x40000000, 0x80000000 },
1611 { /* sentinel */ }
1612};
Marek Vasutddc59352022-12-13 05:46:07 +01001613
1614const struct rproc_att *imx_bootaux_get_hostmap(void)
1615{
1616 return hostmap;
1617}
Peng Fanf19e0e52022-04-29 16:03:14 +08001618#endif