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git01.mediatek.com / filogic / uboot / 7dca6864854c9aa8f8ce65514922d05689e7bbef / . / board / renesas / sh7753evb / lowlevel_init.S
blob: 21987a51e8995f0ac036bcdb94435d5d372f291c [file] [log] [blame]
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +0900[diff] [blame]1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
8#include <version.h>
9#include <asm/processor.h>
10#include <asm/macro.h>
11
12.macro or32, addr, data
13 mov.l \addr, r1
14 mov.l \data, r0
15 mov.l @r1, r2
16 or r2, r0
17 mov.l r0, @r1
18.endm
19
20.macro wait_DBCMD
21 mov.l DBWAIT_A, r0
22 mov.l @r0, r1
23.endm
24
25 .global lowlevel_init
26 .section .spiboot1.text
27 .align 2
28
29lowlevel_init:
30 mov #0, r14
31 mova 2f, r0
32 mov.l PC_MASK, r1
33 tst r0, r1
34 bf 2f
35
36 bra exit_pmb
37 nop
38
39 .align 2
40
41/* If CPU runs on SDRAM (PC=0x5???????) or not. */
42PC_MASK: .long 0x20000000
43
442:
45 mov #1, r14
46
47 mov.l EXPEVT_A, r0
48 mov.l @r0, r0
49 mov.l EXPEVT_POWER_ON_RESET, r1
50 cmp/eq r0, r1
51 bt 1f
52
53 /*
54 * If EXPEVT value is manual reset or tlb multipul-hit,
55 * initialization of DBSC3 is not necessary.
56 */
57 bra exit_ddr
58 nop
59
601:
61 /*------- Reset -------*/
62 write32 MRSTCR0_A, MRSTCR0_D
63 write32 MRSTCR1_A, MRSTCR1_D
64
65 /* For Core Reset */
66 mov.l DBACEN_A, r0
67 mov.l @r0, r0
68 cmp/eq #0, r0
69 bt 3f
70
71 /*
72 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
73 * initialization of DDR3-SDRAM.
74 */
75 bra exit_ddr
76 nop
77
783:
79 /*------- DBSC3 -------*/
80 /* oscillation stabilization time */
81 wait_timer WAIT_OSC_TIME
82
83 /* step 3 */
84 write32 DBKIND_A, DBKIND_D
85
86 /* step 4 */
87 write32 DBCONF_A, DBCONF_D
88 write32 DBTR0_A, DBTR0_D
89 write32 DBTR1_A, DBTR1_D
90 write32 DBTR2_A, DBTR2_D
91 write32 DBTR3_A, DBTR3_D
92 write32 DBTR4_A, DBTR4_D
93 write32 DBTR5_A, DBTR5_D
94 write32 DBTR6_A, DBTR6_D
95 write32 DBTR7_A, DBTR7_D
96 write32 DBTR8_A, DBTR8_D
97 write32 DBTR9_A, DBTR9_D
98 write32 DBTR10_A, DBTR10_D
99 write32 DBTR11_A, DBTR11_D
100 write32 DBTR12_A, DBTR12_D
101 write32 DBTR13_A, DBTR13_D
102 write32 DBTR14_A, DBTR14_D
103 write32 DBTR15_A, DBTR15_D
104 write32 DBTR16_A, DBTR16_D
105 write32 DBTR17_A, DBTR17_D
106 write32 DBTR18_A, DBTR18_D
107 write32 DBTR19_A, DBTR19_D
108 write32 DBRNK0_A, DBRNK0_D
109 write32 DBADJ0_A, DBADJ0_D
110 write32 DBADJ2_A, DBADJ2_D
111
112 /* step 5 */
113 write32 DBCMD_A, DBCMD_RSTL_VAL
114 wait_timer WAIT_30US
115
116 /* step 6 */
117 write32 DBCMD_A, DBCMD_PDEN_VAL
118
119 /* step 7 */
120 write32 DBPDCNT3_A, DBPDCNT3_D
121
122 /* step 8 */
123 write32 DBPDCNT1_A, DBPDCNT1_D
124 write32 DBPDCNT2_A, DBPDCNT2_D
125 write32 DBPDLCK_A, DBPDLCK_D
126 write32 DBPDRGA_A, DBPDRGA_D
127 write32 DBPDRGD_A, DBPDRGD_D
128
129 /* step 9 */
130 wait_timer WAIT_30US
131
132 /* step 10 */
133 write32 DBPDCNT0_A, DBPDCNT0_D
134
135 /* step 11 */
136 wait_timer WAIT_30US
137 wait_timer WAIT_30US
138
139 /* step 12 */
140 write32 DBCMD_A, DBCMD_WAIT_VAL
141 wait_DBCMD
142
143 /* step 13 */
144 write32 DBCMD_A, DBCMD_RSTH_VAL
145 wait_DBCMD
146
147 /* step 14 */
148 write32 DBCMD_A, DBCMD_WAIT_VAL
149 write32 DBCMD_A, DBCMD_WAIT_VAL
150 write32 DBCMD_A, DBCMD_WAIT_VAL
151 write32 DBCMD_A, DBCMD_WAIT_VAL
152
153 /* step 15 */
154 write32 DBCMD_A, DBCMD_PDXT_VAL
155
156 /* step 16 */
157 write32 DBCMD_A, DBCMD_MRS2_VAL
158
159 /* step 17 */
160 write32 DBCMD_A, DBCMD_MRS3_VAL
161
162 /* step 18 */
163 write32 DBCMD_A, DBCMD_MRS1_VAL
164
165 /* step 19 */
166 write32 DBCMD_A, DBCMD_MRS0_VAL
167 write32 DBPDNCNF_A, DBPDNCNF_D
168
169 /* step 20 */
170 write32 DBCMD_A, DBCMD_ZQCL_VAL
171
172 write32 DBCMD_A, DBCMD_REF_VAL
173 write32 DBCMD_A, DBCMD_REF_VAL
174 wait_DBCMD
175
176 /* step 21 */
177 write32 DBCALTR_A, DBCALTR_D
178
179 /* step 22 */
180 write32 DBRFCNF0_A, DBRFCNF0_D
181 write32 DBRFCNF1_A, DBRFCNF1_D
182 write32 DBRFCNF2_A, DBRFCNF2_D
183
184 /* step 23 */
185 write32 DBCALCNF_A, DBCALCNF_D
186
187 /* step 24 */
188 write32 DBRFEN_A, DBRFEN_D
189 write32 DBCMD_A, DBCMD_SRXT_VAL
190
191 /* step 25 */
192 write32 DBACEN_A, DBACEN_D
193
194 /* step 26 */
195 wait_DBCMD
196
197 bra exit_ddr
198 nop
199
200 .align 2
201
202EXPEVT_A: .long 0xff000024
203EXPEVT_POWER_ON_RESET: .long 0x00000000
204
205/*------- Reset -------*/
206MRSTCR0_A: .long 0xffd50030
207MRSTCR0_D: .long 0xfe1ffe7f
208MRSTCR1_A: .long 0xffd50034
209MRSTCR1_D: .long 0xfff3ffff
210
211/*------- DBSC3 -------*/
212DBCMD_A: .long 0xfe800018
213DBKIND_A: .long 0xfe800020
214DBCONF_A: .long 0xfe800024
215DBTR0_A: .long 0xfe800040
216DBTR1_A: .long 0xfe800044
217DBTR2_A: .long 0xfe800048
218DBTR3_A: .long 0xfe800050
219DBTR4_A: .long 0xfe800054
220DBTR5_A: .long 0xfe800058
221DBTR6_A: .long 0xfe80005c
222DBTR7_A: .long 0xfe800060
223DBTR8_A: .long 0xfe800064
224DBTR9_A: .long 0xfe800068
225DBTR10_A: .long 0xfe80006c
226DBTR11_A: .long 0xfe800070
227DBTR12_A: .long 0xfe800074
228DBTR13_A: .long 0xfe800078
229DBTR14_A: .long 0xfe80007c
230DBTR15_A: .long 0xfe800080
231DBTR16_A: .long 0xfe800084
232DBTR17_A: .long 0xfe800088
233DBTR18_A: .long 0xfe80008c
234DBTR19_A: .long 0xfe800090
235DBRNK0_A: .long 0xfe800100
236DBPDCNT0_A: .long 0xfe800200
237DBPDCNT1_A: .long 0xfe800204
238DBPDCNT2_A: .long 0xfe800208
239DBPDCNT3_A: .long 0xfe80020c
240DBPDLCK_A: .long 0xfe800280
241DBPDRGA_A: .long 0xfe800290
242DBPDRGD_A: .long 0xfe8002a0
243DBADJ0_A: .long 0xfe8000c0
244DBADJ2_A: .long 0xfe8000c8
245DBRFCNF0_A: .long 0xfe8000e0
246DBRFCNF1_A: .long 0xfe8000e4
247DBRFCNF2_A: .long 0xfe8000e8
248DBCALCNF_A: .long 0xfe8000f4
249DBRFEN_A: .long 0xfe800014
250DBACEN_A: .long 0xfe800010
251DBWAIT_A: .long 0xfe80001c
252DBCALTR_A: .long 0xfe8000f8
253DBPDNCNF_A: .long 0xfe800180
254
255WAIT_OSC_TIME: .long 6000
256WAIT_30US: .long 13333
257
258DBCMD_RSTL_VAL: .long 0x20000000
259DBCMD_PDEN_VAL: .long 0x1000d73c
260DBCMD_WAIT_VAL: .long 0x0000d73c
261DBCMD_RSTH_VAL: .long 0x2100d73c
262DBCMD_PDXT_VAL: .long 0x110000c8
263DBCMD_MRS0_VAL: .long 0x28000930
264DBCMD_MRS1_VAL: .long 0x29000004
265DBCMD_MRS2_VAL: .long 0x2a000008
266DBCMD_MRS3_VAL: .long 0x2b000000
267DBCMD_ZQCL_VAL: .long 0x03000200
268DBCMD_REF_VAL: .long 0x0c000000
269DBCMD_SRXT_VAL: .long 0x19000000
270DBKIND_D: .long 0x00000007
271DBCONF_D: .long 0x0f030a01
272DBTR0_D: .long 0x00000007
273DBTR1_D: .long 0x00000006
274DBTR2_D: .long 0x00000000
275DBTR3_D: .long 0x00000007
276DBTR4_D: .long 0x00070007
277DBTR5_D: .long 0x0000001b
278DBTR6_D: .long 0x00000014
279DBTR7_D: .long 0x00000004
280DBTR8_D: .long 0x00000014
281DBTR9_D: .long 0x00000004
282DBTR10_D: .long 0x00000008
283DBTR11_D: .long 0x00000007
284DBTR12_D: .long 0x0000000e
285DBTR13_D: .long 0x000000a0
286DBTR14_D: .long 0x00060006
287DBTR15_D: .long 0x00000003
288DBTR16_D: .long 0x00160002
289DBTR17_D: .long 0x000c0000
290DBTR18_D: .long 0x00000200
291DBTR19_D: .long 0x00000040
292DBRNK0_D: .long 0x00000001
293DBPDCNT0_D: .long 0x00000001
294DBPDCNT1_D: .long 0x00000001
295DBPDCNT2_D: .long 0x00000000
296DBPDCNT3_D: .long 0x00004010
297DBPDLCK_D: .long 0x0000a55a
298DBPDRGA_D: .long 0x00000028
299DBPDRGD_D: .long 0x00017100
300
301DBADJ0_D: .long 0x00010000
302DBADJ2_D: .long 0x18061806
303DBRFCNF0_D: .long 0x000001ff
304DBRFCNF1_D: .long 0x00081040
305DBRFCNF2_D: .long 0x00000000
306DBCALCNF_D: .long 0x0000ffff
307DBRFEN_D: .long 0x00000001
308DBACEN_D: .long 0x00000001
309DBCALTR_D: .long 0x08200820
310DBPDNCNF_D: .long 0x00000001
311
312 .align 2
313exit_ddr:
314#if defined(CONFIG_SH_32BIT)
315 /*------- set PMB -------*/
316 write32 PASCR_A, PASCR_29BIT_D
317 write32 MMUCR_A, MMUCR_D
318
319 /*****************************************************************
320 * ent virt phys v sz c wt
321 * 0 0xa0000000 0x00000000 1 128M 0 1
322 * 1 0xa8000000 0x48000000 1 128M 0 1
323 * 5 0x88000000 0x48000000 1 128M 1 1
324 */
325 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
326 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
327 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
328 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
329 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
330 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
331
332 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
333 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
334 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
335 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
336 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
337 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
338 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
339 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
340 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
341 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
342 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
343 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
344 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
345
346 write32 PASCR_A, PASCR_INIT
347 mov.l DUMMY_ADDR, r0
348 icbi @r0
349#endif /* if defined(CONFIG_SH_32BIT) */
350
351exit_pmb:
352 /* CPU is running on ILRAM? */
353 mov r14, r0
354 tst #1, r0
355 bt 1f
356
357 mov.l _stack_ilram, r15
358 mov.l _spiboot_main, r0
359100: bsrf r0
360 nop
361
362 .align 2
363_spiboot_main: .long (spiboot_main - (100b + 4))
364_stack_ilram: .long 0xe5204000
365
3661:
367 write32 CCR_A, CCR_D
368
369 rts
370 nop
371
372 .align 2
373
374#if defined(CONFIG_SH_32BIT)
375/*------- set PMB -------*/
376PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
377PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
378PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
379PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
380PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
381PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
382PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
383PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
384PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
385PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
386PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
387PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
388PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
389PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
390PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
391PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
392
393PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
394PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
395PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
396PMB_ADDR_NOT_USE_D: .long 0x00000000
397
398PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
399PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
400PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
401
402/* ppn ub v s1 s0 c wt */
403PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
404PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
405PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
406
407PASCR_A: .long 0xff000070
408DUMMY_ADDR: .long 0xa0000000
409PASCR_29BIT_D: .long 0x00000000
410PASCR_INIT: .long 0x80000080
411MMUCR_A: .long 0xff000010
412MMUCR_D: .long 0x00000004 /* clear ITLB */
413#endif /* CONFIG_SH_32BIT */
414
415CCR_A: .long CCR
416CCR_D: .long CCR_CACHE_INIT