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git01.mediatek.com / filogic / uboot / 7dc4e85f53c03110ce27ec0b5599aaff1afc41eb / . / configs / chromebook_link_defconfig
blob: 9cf7b0eab763dc916cca9ff26895e826a085b219 [file] [log] [blame]
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]1CONFIG_X86=y
Simon Glass062b9b62015-09-08 17:52:45 -0600[diff] [blame]2CONFIG_SYS_MALLOC_F_LEN=0x1800
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]3CONFIG_DM_I2C=y
Bin Meng03b341b2015-04-27 23:22:24 +0800[diff] [blame]4CONFIG_VENDOR_GOOGLE=y
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]5CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]6CONFIG_TARGET_CHROMEBOOK_LINK=y
Bin Meng21666cf2015-10-11 21:37:36 -0700[diff] [blame]7CONFIG_ENABLE_MRC_CACHE=y
Bin Meng6dd8ddc2016-03-21 06:47:40 -0700[diff] [blame]8CONFIG_HAVE_MRC=y
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]9CONFIG_SMP=y
Bin Meng4de38862015-07-06 16:31:33 +0800[diff] [blame]10CONFIG_HAVE_VGA_BIOS=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]11CONFIG_FIT=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]12CONFIG_BOOTSTAGE=y
13CONFIG_BOOTSTAGE_REPORT=y
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]14CONFIG_CMD_CPU=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]15# CONFIG_CMD_IMLS is not set
16# CONFIG_CMD_FLASH is not set
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]17CONFIG_CMD_GPIO=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]18# CONFIG_CMD_SETEXPR is not set
19# CONFIG_CMD_NFS is not set
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]20CONFIG_CMD_BOOTSTAGE=y
Simon Glass347a6222015-08-22 18:31:39 -0600[diff] [blame]21CONFIG_CMD_TPM=y
Simon Glass81ab5472015-08-22 18:31:43 -0600[diff] [blame]22CONFIG_CMD_TPM_TEST=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]23CONFIG_OF_CONTROL=y
Simon Glass20c6a182016-01-17 16:11:49 -0700[diff] [blame]24CONFIG_REGMAP=y
25CONFIG_SYSCON=y
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]26CONFIG_CPU=y
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]27CONFIG_SYS_I2C_INTEL=y
Simon Glassdfb7c6c2015-07-27 15:47:22 -0600[diff] [blame]28CONFIG_CMD_CROS_EC=y
29CONFIG_CROS_EC=y
30CONFIG_CROS_EC_LPC=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]31CONFIG_SPI_FLASH=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]32CONFIG_SPI_FLASH_GIGADEVICE=y
33CONFIG_SPI_FLASH_MACRONIX=y
34CONFIG_SPI_FLASH_WINBOND=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]35CONFIG_DM_PCI=y
36CONFIG_DM_RTC=y
Simon Glassf2dd4702015-10-18 19:51:27 -0600[diff] [blame]37CONFIG_DEBUG_UART=y
38CONFIG_DEBUG_UART_BASE=0x3f8
39CONFIG_DEBUG_UART_CLOCK=1843200
40CONFIG_DEBUG_UART_BOARD_INIT=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]41CONFIG_SYS_NS16550=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]42CONFIG_ICH_SPI=y
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]43CONFIG_TIMER=y
Simon Glass8b6216a2015-08-22 18:31:20 -0600[diff] [blame]44CONFIG_TPM_TIS_LPC=y
Simon Glass28debcd2016-01-17 16:11:43 -0700[diff] [blame]45CONFIG_USB=y
46CONFIG_DM_USB=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]47CONFIG_VIDEO_VESA=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]48CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
49CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
50CONFIG_USE_PRIVATE_LIBGCC=y
Simon Glass8b6216a2015-08-22 18:31:20 -0600[diff] [blame]51CONFIG_TPM=y