Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Configuration settings for the Espresso7420 board. |
| 4 | * Copyright (C) 2016 Samsung Electronics |
| 5 | * Thomas Abraham <thomas.ab@samsung.com> |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_EXYNOS7420_COMMON_H |
| 9 | #define __CONFIG_EXYNOS7420_COMMON_H |
| 10 | |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 11 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
| 12 | #include <linux/sizes.h> |
| 13 | |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 14 | /* Miscellaneous configurable options */ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 15 | |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 16 | /* select serial console configuration */ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 17 | |
Thomas Abraham | f1855fc | 2016-11-16 18:49:16 +0530 | [diff] [blame] | 18 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 19 | |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 20 | /* select serial console configuration */ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 21 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 22 | #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 23 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 24 | #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 25 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 26 | #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 27 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 28 | #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 29 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 30 | #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 31 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 32 | #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 33 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 34 | #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 35 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 36 | #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 37 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE |
| 38 | |
| 39 | /* Configuration of ENV Blocks */ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 40 | |
| 41 | #define BOOT_TARGET_DEVICES(func) \ |
| 42 | func(MMC, mmc, 1) \ |
| 43 | func(MMC, mmc, 0) \ |
| 44 | |
| 45 | #ifndef MEM_LAYOUT_ENV_SETTINGS |
| 46 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 47 | "bootm_size=0x10000000\0" \ |
| 48 | "kernel_addr_r=0x42000000\0" \ |
| 49 | "fdt_addr_r=0x43000000\0" \ |
| 50 | "ramdisk_addr_r=0x43300000\0" \ |
| 51 | "scriptaddr=0x50000000\0" \ |
| 52 | "pxefile_addr_r=0x51000000\0" |
| 53 | #endif |
| 54 | |
| 55 | #ifndef EXYNOS_DEVICE_SETTINGS |
| 56 | #define EXYNOS_DEVICE_SETTINGS \ |
| 57 | "stdin=serial\0" \ |
| 58 | "stdout=serial\0" \ |
| 59 | "stderr=serial\0" |
| 60 | #endif |
| 61 | |
| 62 | #ifndef EXYNOS_FDTFILE_SETTING |
| 63 | #define EXYNOS_FDTFILE_SETTING |
| 64 | #endif |
| 65 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 66 | #define CFG_EXTRA_ENV_SETTINGS \ |
Thomas Abraham | d23cb31 | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 67 | EXYNOS_DEVICE_SETTINGS \ |
| 68 | EXYNOS_FDTFILE_SETTING \ |
| 69 | MEM_LAYOUT_ENV_SETTINGS |
| 70 | |
| 71 | #endif /* __CONFIG_EXYNOS7420_COMMON_H */ |